1 /* 2 * Copyright (c) 2025 Intel Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_ETHERNET_ETH_INTEL_IGC_PRIV_H_ 8 #define ZEPHYR_DRIVERS_ETHERNET_ETH_INTEL_IGC_PRIV_H_ 9 10 #include <zephyr/device.h> 11 #include <zephyr/kernel.h> 12 #include <zephyr/drivers/pcie/pcie.h> 13 #include <zephyr/drivers/pcie/msi.h> 14 #include <zephyr/sys/util.h> 15 #include <zephyr/drivers/ethernet/eth_intel_plat.h> 16 17 #define ETH_MAX_FRAME_SZ 2048 18 #define INTEL_IGC_MAX_QCNT 4 19 #define ETH_IGC_NUM_MISC 1 20 #define RAH_QSEL_SHIFT 18 21 #define RAH_QSEL_ENABLE BIT(28) 22 #define RAH_QSEL_MASK GENMASK(19, 18) 23 #define RAH_ASEL_MASK GENMASK(17, 16) 24 #define RAH_ASEL_SRC_ADDR BIT(16) 25 #define INTEL_IGC_RAH_AV BIT(31) 26 #define INTEL_IGC_DEF_MAC_ADDR 0xC9A000 27 28 /* Device Control Register */ 29 #define INTEL_IGC_CTRL 0x00000 30 #define INTEL_IGC_CTRL_GIO_MASTER_DISABLE BIT(2) 31 #define INTEL_IGC_CTRL_SLU BIT(6) 32 #define INTEL_IGC_CTRL_FRCSPD BIT(11) 33 #define INTEL_IGC_CTRL_FRCDPX BIT(12) 34 #define INTEL_IGC_CTRL_RST BIT(26) 35 #define INTEL_IGC_CTRL_RFCE BIT(27) 36 #define INTEL_IGC_CTRL_TFCE BIT(28) 37 #define INTEL_IGC_CTRL_EXT_DRV_LOAD BIT(28) 38 #define INTEL_IGC_CTRL_DEV_RST BIT(29) 39 #define INTEL_IGC_CTRL_VME BIT(30) 40 #define INTEL_IGC_CTRL_PHY_RST BIT(31) 41 42 /* Device Status Register */ 43 #define INTEL_IGC_STATUS 0x00008 44 #define INTEL_IGC_STATUS_FD BIT(0) 45 #define INTEL_IGC_STATUS_LU BIT(1) 46 #define INTEL_IGC_STATUS_TXOFF BIT(4) 47 #define INTEL_IGC_STATUS_SPEED_100 BIT(6) 48 #define INTEL_IGC_STATUS_SPEED_1000 BIT(7) 49 #define INTEL_IGC_STATUS_GIO_MASTER_ENABLE BIT(19) 50 #define INTEL_IGC_STATUS_SPEED_MASK GENMASK(7, 6) 51 52 /* Extended Device Control Register */ 53 #define INTEL_IGC_CTRL_EXT 0x00018 54 #define INTEL_IGC_CTRL_EXT_DRV_LOAD BIT(28) 55 56 /* Internal Rx Packet Buffer Size */ 57 #define INTEL_IGC_RXPBS 0x02404 58 #define INTEL_IGC_RXPBS_RXPBSIZE_MASK GENMASK(5, 0) 59 #define INTEL_IGC_RXPBS_RXPBSIZE_DEFAULT 0x000000A2 60 61 /* Internal Tx Packet Buffer Size*/ 62 #define INTEL_IGC_TXPBS 0x03404 63 #define INTEL_IGC_TXPBS_TXPBSIZE_DEFAULT 0x04000014 64 65 /* Interrupt Cause Read */ 66 #define INTEL_IGC_ICR 0x01500 67 68 /* Interrupt Cause Set */ 69 #define INTEL_IGC_ICS 0x01504 70 71 /* Interrupt Mask Set/Read */ 72 #define INTEL_IGC_IMS 0x01508 73 74 /* Interrupt Mask Clear */ 75 #define INTEL_IGC_IMC 0x0150C 76 77 #define INTEL_IGC_TXDW BIT(0) 78 #define INTEL_IGC_LSC BIT(2) 79 #define INTEL_IGC_RXDMT0 BIT(4) 80 #define INTEL_IGC_RX_MISS BIT(6) 81 #define INTEL_IGC_RXDW BIT(7) 82 #define INTEL_IGC_TIME_SYNC BIT(19) 83 #define INTEL_IGC_DRSTA BIT(30) 84 #define INTEL_IGC_INTA BIT(31) 85 86 /* General Purpose Interrupt Enable */ 87 #define INTEL_IGC_GPIE 0x01514 88 #define INTEL_IGC_GPIE_NSICR BIT(0) 89 #define INTEL_IGC_GPIE_MSIX_MODE BIT(4) 90 #define INTEL_IGC_GPIE_EIAME BIT(30) 91 #define INTEL_IGC_GPIE_PBA BIT(31) 92 93 /* Extended Interrupt Cause Set */ 94 #define INTEL_IGC_EICS 0x01520 95 96 /* Extended Interrupt Mask Set/Read */ 97 #define INTEL_IGC_EIMS 0x01524 98 99 /* Extended Interrupt Mask Clear */ 100 #define INTEL_IGC_EIMC 0x01528 101 102 /* Extended Interrupt Auto Clear */ 103 #define INTEL_IGC_EIAC 0x0152C 104 105 /* Extended Interrupt Auto Mask */ 106 #define INTEL_IGC_EIAM 0x01530 107 108 /* Extended Interrupt Cause read */ 109 #define INTEL_IGC_EICR 0x01580 110 111 /* Interrupt Throttle */ 112 #define INTEL_IGC_EITR_BASE_ADDR 0x01680 113 #define INTEL_IGC_EITR(n) (INTEL_IGC_EITR_BASE_ADDR + (n * 4)) 114 115 /* Interrupt Vector Allocation */ 116 #define INTEL_IGC_IVAR_BASE_ADDR 0x01700 117 #define INTEL_IGC_IVAR(n) (INTEL_IGC_IVAR_BASE_ADDR + (n * 4)) 118 119 /* Interrupt Vector Allocation MISC */ 120 #define INTEL_IGC_IVAR_MISC 0x01740 121 #define INTEL_IGC_IVAR_INT_VALID_BIT BIT(7) 122 #define INTEL_IGC_IVAR_MSI_CLEAR_RX0_RX2 0xFFFFFF00 123 #define INTEL_IGC_IVAR_MSI_CLEAR_TX0_TX2 0xFFFF00FF 124 #define INTEL_IGC_IVAR_MSI_CLEAR_RX1_RX3 0xFF00FFFF 125 #define INTEL_IGC_IVAR_MSI_CLEAR_TX1_TX3 0x00FFFFFF 126 127 /* Receive Control */ 128 #define INTEL_IGC_RCTL 0x00100 129 #define INTEL_IGC_RCTL_EN BIT(1) 130 #define INTEL_IGC_RCTL_SBP BIT(2) 131 #define INTEL_IGC_RCTL_UPE BIT(3) 132 #define INTEL_IGC_RCTL_MPE BIT(4) 133 #define INTEL_IGC_RCTL_LPE BIT(5) 134 #define INTEL_IGC_RCTL_LBM_MAC BIT(6) 135 #define INTEL_IGC_RCTL_BAM BIT(15) 136 #define INTEL_IGC_RCTL_VFE BIT(18) 137 #define INTEL_IGC_RCTL_CFIEN BIT(19) 138 #define INTEL_IGC_RCTL_PADSMALL BIT(21) 139 #define INTEL_IGC_RCTL_DPF BIT(22) 140 #define INTEL_IGC_RCTL_PMCF BIT(23) 141 #define INTEL_IGC_RCTL_SECRC BIT(26) 142 #define INTEL_IGC_RCTL_MO_SHIFT 12 143 #define INTEL_IGC_RCTL_SZ_2048 0x0 144 #define INTEL_IGC_RCTL_SZ_1024 GENMASK(16, 16) 145 #define INTEL_IGC_RCTL_SZ_512 GENMASK(17, 17) 146 #define INTEL_IGC_RCTL_SZ_256 GENMASK(17, 16) 147 #define INTEL_IGC_RCTL_LBM_TCVR GENMASK(7, 6) 148 149 /* Split and Replication Receive Control */ 150 #define INTEL_IGC_SRRCTL_BASE 0x0C00C 151 #define INTEL_IGC_SRRCTL_OFFSET 0x40 152 #define INTEL_IGC_SRRCTL(n) (INTEL_IGC_SRRCTL_BASE + (INTEL_IGC_SRRCTL_OFFSET * (n))) 153 #define INTEL_IGC_SRRCTL_BSIZEPKT_MASK GENMASK(6, 0) 154 155 /* Convert as 1024 Bytes resolution */ 156 #define INTEL_IGC_SRRCTL_BSIZEPKT(x) FIELD_PREP(INTEL_IGC_SRRCTL_BSIZEPKT_MASK, (x) / 1024) 157 #define INTEL_IGC_SRRCTL_BSIZEHDR_MASK GENMASK(13, 8) 158 159 /* Covert as 64 Bytes resolution */ 160 #define INTEL_IGC_SRRCTL_BSIZEHDR(x) FIELD_PREP(INTEL_IGC_SRRCTL_BSIZEHDR_MASK, (x) / 64) 161 #define INTEL_IGC_RXBUFFER_256 256 162 #define INTEL_IGC_SRRCTL_DESCTYPE_ADV_ONEBUF BIT(25) 163 #define INTEL_IGC_SRRCTL_DROP_EN BIT(31) 164 165 /* Receive Descriptor Base Address Low */ 166 #define INTEL_IGC_RDBAL_BASE_ADDR 0x0C000 167 #define INTEL_IGC_RDBAL_OFFSET 0x40 168 #define INTEL_IGC_RDBAL(n) (INTEL_IGC_RDBAL_BASE_ADDR + (INTEL_IGC_RDBAL_OFFSET * (n))) 169 170 /* Receive Descriptor Base Address High */ 171 #define INTEL_IGC_RDBAH_BASE_ADDR 0x0C004 172 #define INTEL_IGC_RDBAH_OFFSET 0x40 173 #define INTEL_IGC_RDBAH(n) (INTEL_IGC_RDBAH_BASE_ADDR + (INTEL_IGC_RDBAH_OFFSET * (n))) 174 175 /* Receive Descriptor Ring Length */ 176 #define INTEL_IGC_RDLEN_BASE_ADDR 0x0C008 177 #define INTEL_IGC_RDLEN_OFFSET 0x40 178 #define INTEL_IGC_RDLEN(n) (INTEL_IGC_RDLEN_BASE_ADDR + (INTEL_IGC_RDLEN_OFFSET * (n))) 179 180 /* Receive Descriptor Head */ 181 #define INTEL_IGC_RDH_BASE_ADDR 0x0C010 182 #define INTEL_IGC_RDH_OFFSET 0x40 183 #define INTEL_IGC_RDH(n) (INTEL_IGC_RDH_BASE_ADDR + (INTEL_IGC_RDH_OFFSET * (n))) 184 185 /* Receive Descriptor Tail */ 186 #define INTEL_IGC_RDT_BASE_ADDR 0x0C018 187 #define INTEL_IGC_RDT_OFFSET 0x40 188 #define INTEL_IGC_RDT(n) (INTEL_IGC_RDT_BASE_ADDR + (INTEL_IGC_RDT_OFFSET * (n))) 189 190 /* Receive Descriptor Control */ 191 #define INTEL_IGC_RXDCTL_BASE_ADDR 0x0C028 192 #define INTEL_IGC_RXDCTL_OFFSET 0x40 193 #define INTEL_IGC_RXDCTL(n) (INTEL_IGC_RXDCTL_BASE_ADDR + (INTEL_IGC_RXDCTL_OFFSET * (n))) 194 #define INTEL_IGC_RXDCTL_QUEUE_ENABLE BIT(25) 195 #define INTEL_IGC_RXDCTL_SWFLUSH BIT(26) 196 197 #define INTEL_IGC_RX_THRESH_RESET GENMASK(31, 21) 198 #define INTEL_IGC_RX_PTHRESH_VAL 8 199 #define INTEL_IGC_RX_HTHRESH_VAL 8 200 #define INTEL_IGC_RX_WTHRESH_VAL 8 201 #define INTEL_IGC_RX_PTHRESH_SHIFT 0 202 #define INTEL_IGC_RX_HTHRESH_SHIFT 8 203 #define INTEL_IGC_RX_WTHRESH_SHIFT 16 204 205 /* Receive Queue Drop Packet Count */ 206 #define INTEL_IGC_RQDPC_BASE_ADDR 0x0C030 207 #define INTEL_IGC_RQDPC_OFFSET 0x40 208 #define INTEL_IGC_RQDPC(n) (INTEL_IGC_RQDPC_BASE_ADDR + (INTEL_IGC_RQDPC_OFFSET * (n))) 209 210 /* Receive Checksum Control */ 211 #define INTEL_IGC_RXCSUM 0x05000 212 #define INTEL_IGC_RXCSUM_CRCOFL BIT(11) 213 #define INTEL_IGC_RXCSUM_PCSD BIT(13) 214 215 /* Receive Long Packet Maximum Length */ 216 #define INTEL_IGC_RLPML 0x05004 217 218 /* Receive Filter Control */ 219 #define INTEL_IGC_RFCTL 0x05008 220 #define INTEL_IGC_RFCTL_IPV6_EX_DIS BIT(16) 221 #define INTEL_IGC_RFCTL_LEF BIT(18) 222 223 /* Collision related config parameters */ 224 #define INTEL_IGC_TCTL_CT_SHIFT 4 225 #define INTEL_IGC_COLLISION_THRESHOLD 15 226 227 /* Transmit Control Register */ 228 #define INTEL_IGC_TCTL 0x00400 229 #define INTEL_IGC_TCTL_EN BIT(1) 230 #define INTEL_IGC_TCTL_PSP BIT(3) 231 #define INTEL_IGC_TCTL_RTLC BIT(24) 232 #define INTEL_IGC_TCTL_CT GENMASK(11, 4) 233 #define INTEL_IGC_TCTL_COLD GENMASK(21, 12) 234 235 /* Transmit Descriptor Base Address Low */ 236 #define INTEL_TDBAL_BASE_ADDR 0x0E000 237 #define INTEL_TDBAL_OFFSET 0x40 238 #define INTEL_IGC_TDBAL(n) (INTEL_TDBAL_BASE_ADDR + (INTEL_TDBAL_OFFSET * (n))) 239 240 /* Transmit Descriptor Base Address High */ 241 #define INTEL_TDBAH_BASE_ADDR 0x0E004 242 #define INTEL_TDBAH_OFFSET 0x40 243 #define INTEL_IGC_TDBAH(n) (INTEL_TDBAH_BASE_ADDR + (INTEL_TDBAH_OFFSET * (n))) 244 245 /* Transmit Descriptor Ring Length */ 246 #define INTEL_TDLEN_BASE_ADDR 0x0E008 247 #define INTEL_TDLEN_OFFSET 0x40 248 #define INTEL_IGC_TDLEN(n) (INTEL_TDLEN_BASE_ADDR + (INTEL_TDLEN_OFFSET * (n))) 249 250 /* Transmit Descriptor Head */ 251 #define INTEL_TDH_BASE_ADDR 0x0E010 252 #define INTEL_TDH_OFFSET 0x40 253 #define INTEL_IGC_TDH(n) (INTEL_TDH_BASE_ADDR + (INTEL_TDH_OFFSET * (n))) 254 255 /* Transmit Descriptor Tail */ 256 #define INTEL_TDT_BASE_ADDR 0x0E018 257 #define INTEL_TDT_OFFSET 0x40 258 #define INTEL_IGC_TDT(n) (INTEL_TDT_BASE_ADDR + (INTEL_TDT_OFFSET * (n))) 259 260 /* Transmit Descriptor Control */ 261 #define INTEL_TXDCTL_BASE_ADDR 0x0E028 262 #define INTEL_TXDCTL_OFFSET 0x40 263 #define INTEL_IGC_TXDCTL(n) (INTEL_TXDCTL_BASE_ADDR + (INTEL_TXDCTL_OFFSET * (n))) 264 #define INTEL_IGC_TXDCTL_QUEUE_ENABLE BIT(25) 265 266 #define INTEL_IGC_TX_PTHRESH_VAL 8 267 #define INTEL_IGC_TX_HTHRESH_VAL 8 268 #define INTEL_IGC_TX_WTHRESH_VAL 8 269 #define INTEL_IGC_TX_PTHRESH_SHIFT 0 270 #define INTEL_IGC_TX_HTHRESH_SHIFT 8 271 #define INTEL_IGC_TX_WTHRESH_SHIFT 16 272 #define INTEL_IGC_TX_DESC_TYPE 0x3 273 274 /* Statistics Register Descriptions */ 275 #define INTEL_IGC_CRCERRS 0x04000 276 #define INTEL_IGC_ALGNERRC 0x04004 277 #define INTEL_IGC_RXERRC 0x0400C 278 #define INTEL_IGC_MPC 0x04010 279 #define INTEL_IGC_SCC 0x04014 280 #define INTEL_IGC_ECOL 0x04018 281 #define INTEL_IGC_MCC 0x0401C 282 #define INTEL_IGC_LATECOL 0x04020 283 #define INTEL_IGC_COLC 0x04028 284 #define INTEL_IGC_RERC 0x0402C 285 #define INTEL_IGC_DC 0x04030 286 #define INTEL_IGC_TNCRS 0x04034 287 #define INTEL_IGC_HTDPMC 0x0403C 288 #define INTEL_IGC_RLEC 0x04040 289 #define INTEL_IGC_XONRXC 0x04048 290 #define INTEL_IGC_XONTXC 0x0404C 291 #define INTEL_IGC_XOFFRXC 0x04050 292 #define INTEL_IGC_XOFFTXC 0x04054 293 #define INTEL_IGC_FCRUC 0x04058 294 #define INTEL_IGC_PRC64 0x0405C 295 #define INTEL_IGC_PRC127 0x04060 296 #define INTEL_IGC_PRC255 0x04064 297 #define INTEL_IGC_PRC511 0x04068 298 #define INTEL_IGC_PRC1023 0x0406C 299 #define INTEL_IGC_PRC1522 0x04070 300 #define INTEL_IGC_GPRC 0x04074 301 #define INTEL_IGC_BPRC 0x04078 302 #define INTEL_IGC_MPRC 0x0407C 303 #define INTEL_IGC_GPTC 0x04080 304 #define INTEL_IGC_GORCL 0x04088 305 #define INTEL_IGC_GORCH 0x0408C 306 #define INTEL_IGC_GOTCL 0x04090 307 #define INTEL_IGC_GOTCH 0x04094 308 #define INTEL_IGC_RNBC 0x040A0 309 #define INTEL_IGC_RUC 0x040A4 310 #define INTEL_IGC_RFC 0x040A8 311 #define INTEL_IGC_ROC 0x040AC 312 #define INTEL_IGC_RJC 0x040B0 313 #define INTEL_IGC_MGTPRC 0x040B4 314 #define INTEL_IGC_MGTPDC 0x040B8 315 #define INTEL_IGC_MGTPTC 0x040BC 316 #define INTEL_IGC_TORL 0x040C0 317 #define INTEL_IGC_TORH 0x040C4 318 #define INTEL_IGC_TOTL 0x040C8 319 #define INTEL_IGC_TOTH 0x040CC 320 #define INTEL_IGC_TPR 0x040D0 321 #define INTEL_IGC_TPT 0x040D4 322 #define INTEL_IGC_PTC64 0x040D8 323 #define INTEL_IGC_PTC127 0x040DC 324 #define INTEL_IGC_PTC255 0x040E0 325 #define INTEL_IGC_PTC511 0x040E4 326 #define INTEL_IGC_PTC1023 0x040E8 327 #define INTEL_IGC_PTC1522 0x040EC 328 #define INTEL_IGC_MPTC 0x040F0 329 #define INTEL_IGC_BPTC 0x040F4 330 #define INTEL_IGC_TSCTC 0x040F8 331 #define INTEL_IGC_IAC 0x04100 332 #define INTEL_IGC_RPTHC 0x04104 333 #define INTEL_IGC_TLPIC 0x04148 334 #define INTEL_IGC_RLPIC 0x0414C 335 #define INTEL_IGC_HGPTC 0x04118 336 #define INTEL_IGC_RXDMTC 0x04120 337 #define INTEL_IGC_HGORCL 0x04128 338 #define INTEL_IGC_HGORCH 0x0412C 339 #define INTEL_IGC_HGOTCL 0x04130 340 #define INTEL_IGC_HGOTCH 0x04134 341 #define INTEL_IGC_LENERRS 0x04138 342 #define INTEL_IGC_TQDPC_BASE 0x0E030 343 #define INTEL_IGC_TQDPC_OFFSET 0x40 344 #define INTEL_IGC_TQDPC(n) (INTEL_IGC_TQDPC_BASE + (INTEL_IGC_TQDPC_OFFSET * (n))) 345 346 #define INTEL_IGC_GIO_MASTER_DISABLE_TIMEOUT 800 347 #define INTEL_IGC_RESET_DELAY 1 348 349 #define INTEL_IGC_RAL(i) (((i) <= 15) ? (0x05400 + ((i) * 8)) : (0x054E0 + ((i - 16) * 8))) 350 #define INTEL_IGC_RAH(i) (((i) <= 15) ? (0x05404 + ((i) * 8)) : (0x054E4 + ((i - 16) * 8))) 351 352 typedef void (*eth_config_irq_t)(const struct device *); 353 354 struct eth_intel_igc_intr_info { 355 const struct device *mac; 356 msi_vector_t msi_vector; 357 uint8_t id; 358 }; 359 360 enum eth_igc_mac_filter_mode { 361 DEST_ADDR, /* normal mode */ 362 SRC_ADDR 363 }; 364 365 /** 366 * @brief This Advanced transmit descriptor format is crucial for the transmit DMA. 367 * Field misalignment or size change will break the DMA operation. Modify this 368 * structure with caution. 369 */ 370 union dma_tx_desc { 371 struct { 372 uint64_t data_buf_addr; 373 374 unsigned int data_len: 16; 375 unsigned int ptp1: 4; 376 unsigned int desc_type: 4; 377 unsigned int eop: 1; 378 unsigned int ifcs: 1; 379 unsigned int reserved1: 1; 380 unsigned int rs: 1; 381 unsigned int reserved2: 1; 382 unsigned int dext: 1; 383 unsigned int vle: 1; 384 unsigned int tse: 1; 385 unsigned int dd: 1; 386 unsigned int ts_stat: 1; 387 unsigned int reserved3: 2; 388 unsigned int idx: 1; 389 unsigned int ptp2: 3; 390 unsigned int popts: 6; 391 unsigned int payloadlen: 18; 392 } read; 393 394 struct { 395 uint64_t dma_time_stamp; 396 397 unsigned int reserved1: 32; 398 unsigned int dd: 1; 399 unsigned int ts_stat: 1; 400 unsigned int reserved2: 2; 401 unsigned int reserved3: 28; 402 } writeback; 403 }; 404 405 /** 406 * @brief This Advanced receive descriptor format is crucial for the receive DMA. 407 * Field misalignment or size change will break the DMA operation. Modify this 408 * structure with caution. 409 */ 410 union dma_rx_desc { 411 struct { 412 uint64_t pkt_buf_addr; 413 uint64_t hdr_buf_addr; 414 } read; 415 416 struct { 417 unsigned int rss_type: 4; 418 unsigned int pkt_type: 13; 419 unsigned int reserved1: 2; 420 unsigned int hdr_len: 12; 421 unsigned int sph: 1; 422 unsigned int rss_has_val: 32; 423 424 /* extended status */ 425 unsigned int dd: 1; 426 unsigned int eop: 1; 427 unsigned int reserved2: 1; 428 unsigned int vp: 1; 429 unsigned int udpcs: 1; 430 unsigned int l4cs: 1; 431 unsigned int ipcs: 1; 432 unsigned int pif: 1; 433 unsigned int reserved3: 1; 434 unsigned int vext: 1; 435 unsigned int udpv: 1; 436 unsigned int llint: 1; 437 unsigned int crc_strip: 1; 438 unsigned int smd_type: 2; 439 unsigned int tsip: 1; 440 unsigned int reserved4: 3; 441 unsigned int mc: 1; 442 443 /* extended error */ 444 unsigned int reserved5: 3; 445 unsigned int hbo: 1; 446 unsigned int reserved6: 5; 447 unsigned int l4e: 1; 448 unsigned int ipe: 1; 449 unsigned int rxe: 1; 450 451 unsigned int pkt_len: 16; 452 unsigned int vlan_tag: 16; 453 } writeback; 454 }; 455 456 struct eth_intel_igc_mac_cfg { 457 const struct device *const platform; 458 const struct device *const phy; 459 eth_config_irq_t config_func; 460 uint32_t num_tx_desc; 461 uint32_t num_rx_desc; 462 uint8_t num_queues; 463 uint8_t num_msix; 464 bool random_mac_address; 465 }; 466 467 struct eth_intel_igc_mac_tx { 468 union dma_tx_desc *desc; 469 struct k_sem *sem; 470 uint32_t *ring_wr_ptr; 471 uint32_t *ring_rd_ptr; 472 struct net_buf **frag; 473 struct net_pkt **pkt; 474 }; 475 476 struct eth_intel_igc_mac_rx { 477 union dma_rx_desc *desc; 478 struct k_sem *sem; 479 uint32_t *ring_wr_ptr; 480 uint32_t *ring_rd_ptr; 481 uint8_t *buf; 482 }; 483 484 struct eth_intel_igc_mac_data { 485 struct net_if *iface; 486 const struct device *mac; 487 struct eth_intel_igc_mac_tx tx; 488 struct eth_intel_igc_mac_rx rx; 489 struct k_work tx_work[INTEL_IGC_MAX_QCNT]; 490 struct k_work_delayable rx_work[INTEL_IGC_MAX_QCNT]; 491 struct eth_intel_igc_intr_info *intr_info; 492 uint8_t mac_addr[NET_ETH_ADDR_LEN]; 493 msi_vector_t *msi_vec; 494 #if defined(CONFIG_NET_STATISTICS_ETHERNET) 495 struct net_stats_eth stats; 496 #endif 497 mm_reg_t base; 498 }; 499 500 #endif /* ZEPHYR_DRIVERS_ETHERNET_ETH_INTEL_IGC_PRIV_H_*/ 501