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Searched refs:base_address (Results 1 – 14 of 14) sorted by relevance

/drivers/flash/
A Dflash_cadence_nand_ll.c58 uintptr_t base_address; in cdns_nand_device_info() local
62 base_address = params->nand_base; in cdns_nand_device_info()
561 uint32_t base_address; in cdns_cdma_desc_transfer_finish() local
575 base_address = params->nand_base; in cdns_cdma_desc_transfer_finish()
694 uintptr_t base_address; in cdns_nand_pio_erase() local
699 base_address = params->nand_base; in cdns_nand_pio_erase()
782 uintptr_t base_address; in cdns_nand_pio_write() local
785 base_address = params->nand_base; in cdns_nand_pio_write()
813 uintptr_t base_address; in cdns_nand_pio_read() local
877 uintptr_t base_address; in cdns_generic_send_cmd() local
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A Dsoc_flash_silabs_siwx91x.c17 uintptr_t base_address; member
58 void *location = (void *)(cfg->base_address + offset); in flash_siwx91x_read()
85 ret = sl_si91x_command_to_write_common_flash(cfg->base_address + offset, (void *)buf, len, in flash_siwx91x_write()
110 ret = sl_si91x_command_to_write_common_flash(cfg->base_address + offset, NULL, len, true); in flash_siwx91x_erase()
157 .base_address = DT_REG_ADDR(n), \
/drivers/syscon/
A Dsyscon.c40 uintptr_t base_address; in syscon_generic_read_reg() local
50 base_address = DEVICE_MMIO_GET(dev); in syscon_generic_read_reg()
54 *val = sys_read8(base_address + reg); in syscon_generic_read_reg()
57 *val = sys_read16(base_address + reg); in syscon_generic_read_reg()
60 *val = sys_read32(base_address + reg); in syscon_generic_read_reg()
73 uintptr_t base_address; in syscon_generic_write_reg() local
79 base_address = DEVICE_MMIO_GET(dev); in syscon_generic_write_reg()
83 sys_write8(val, (base_address + reg)); in syscon_generic_write_reg()
86 sys_write16(val, (base_address + reg)); in syscon_generic_write_reg()
89 sys_write32(val, (base_address + reg)); in syscon_generic_write_reg()
/drivers/reset/
A Dreset_intel_socfpga.c29 uintptr_t base_address = DEVICE_MMIO_GET(dev); in reset_intel_soc_status() local
36 value = sys_read32(base_address + offset); in reset_intel_soc_status()
44 uintptr_t base_address = DEVICE_MMIO_GET(dev); in reset_intel_soc_update() local
52 if (sys_test_bit(base_address + offset, regbit) == 0) { in reset_intel_soc_update()
53 sys_set_bit(base_address + offset, regbit); in reset_intel_soc_update()
56 if (sys_test_bit(base_address + offset, regbit) != 0) { in reset_intel_soc_update()
57 sys_clear_bit(base_address + offset, regbit); in reset_intel_soc_update()
/drivers/counter/
A Dcounter_realtek_rts5912.c35 volatile struct timer32_type *base_address; member
54 volatile struct timer32_type *counter = config->base_address; in counter_rts5912_start()
70 volatile struct timer32_type *counter = config->base_address; in counter_rts5912_stop()
90 volatile struct timer32_type *counter = config->base_address; in counter_rts5912_get_value()
101 volatile struct timer32_type *counter = counter_cfg->base_address; in counter_rts5912_set_alarm()
156 volatile struct timer32_type *counter = config->base_address; in counter_rts5912_cancel_alarm()
176 volatile struct timer32_type *counter = config->base_address; in counter_rts5912_get_pending_int()
184 volatile struct timer32_type *counter = config->base_address; in counter_rts5912_get_top_value()
194 volatile struct timer32_type *counter = counter_cfg->base_address; in counter_rts5912_set_top_value()
238 volatile struct timer32_type *counter = config->base_address; in counter_rts5912_isr()
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A Dcounter_realtek_rts5912_slwtmr.c36 volatile struct slwtmr_type *base_address; member
53 volatile struct slwtmr_type *counter = config->base_address; in counter_rts5912_start()
69 volatile struct slwtmr_type *counter = config->base_address; in counter_rts5912_stop()
91 volatile struct slwtmr_type *counter = config->base_address; in counter_rts5912_get_value()
101 volatile struct slwtmr_type *counter = config->base_address; in counter_rts5912_set_alarm()
149 volatile struct slwtmr_type *counter = config->base_address; in counter_rts5912_cancel_alarm()
170 volatile struct slwtmr_type *counter = config->base_address; in counter_rts5912_get_pending_int()
178 volatile struct slwtmr_type *counter = config->base_address; in counter_rts5912_get_top_value()
187 volatile struct slwtmr_type *counter = config->base_address; in counter_rts5912_set_top_value()
227 volatile struct slwtmr_type *counter = config->base_address; in counter_rts5912_isr()
[all …]
A Dcounter_mchp_xec.c37 uint32_t base_address; member
52 _dev->config)->base_address)
329 .base_address = DT_INST_REG_ADDR(inst), \
/drivers/clock_control/
A Dclock_control_rv32m1_pcc.c18 uint32_t base_address; member
22 (((struct rv32m1_pcc_config *)(dev->config))->base_address)
62 .base_address = DT_INST_REG_ADDR(inst) \
A Dclock_control_renesas_cpg_mssr.c19 static void rcar_cpg_reset(uint32_t base_address, uint32_t reg, uint32_t bit) in rcar_cpg_reset() argument
21 rcar_cpg_write(base_address, srcr[reg], BIT(bit)); in rcar_cpg_reset()
22 rcar_cpg_write(base_address, SRSTCLR(reg), BIT(bit)); in rcar_cpg_reset()
25 void rcar_cpg_write(uint32_t base_address, uint32_t reg, uint32_t val) in rcar_cpg_write() argument
27 sys_write32(~val, base_address + CPGWPR); in rcar_cpg_write()
28 sys_write32(val, base_address + reg); in rcar_cpg_write()
33 int rcar_cpg_mstp_clock_endisable(uint32_t base_address, uint32_t module, bool enable) in rcar_cpg_mstp_clock_endisable() argument
43 reg_val = sys_read32(base_address + mstpcr[reg]); in rcar_cpg_mstp_clock_endisable()
50 sys_write32(reg_val, base_address + mstpcr[reg]); in rcar_cpg_mstp_clock_endisable()
52 rcar_cpg_reset(base_address, reg, bit); in rcar_cpg_mstp_clock_endisable()
A Dclock_control_mcux_pcc.c22 uint32_t base_address; member
27 #define DEV_BASE(dev) (((struct mcux_pcc_config *)(dev->config))->base_address)
140 .base_address = DT_INST_REG_ADDR(inst), \
A Dclock_control_renesas_cpg_mssr.h128 void rcar_cpg_write(uint32_t base_address, uint32_t reg, uint32_t val);
130 int rcar_cpg_mstp_clock_endisable(uint32_t base_address, uint32_t module, bool enable);
/drivers/audio/
A Ddmic_mcux.c36 DMIC_Type *base_address; member
94 DMIC_EnableChannnel(drv_data->base_address, mask); in dmic_mcux_activate_channels()
97 drv_data->base_address->CHANEN &= ~mask; in dmic_mcux_activate_channels()
126 DMIC_EnableChannelDma(drv_data->base_address, in dmic_mcux_enable_dma()
308 DMIC_FifoGetAddress(drv_data->base_address, hw_chan); in dmic_mcux_setup_dma()
392 DMIC_Init(drv_data->base_address); in mcux_dmic_init()
393 DMIC_Use2fs(drv_data->base_address, config->use2fs); in mcux_dmic_init()
396 DMIC_SetIOCFG(drv_data->base_address, kDMIC_PdmDual); in mcux_dmic_init()
435 DMIC_DeInit(drv_data->base_address); in dmic_mcux_configure()
613 DMIC_DeInit(drv_data->base_address); in dmic_mcux_trigger()
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/drivers/interrupt_controller/
A Dintc_intel_vtd.c39 uintptr_t base_address = DEVICE_MMIO_GET(dev); in vtd_write_reg32() local
41 sys_write32(value, (base_address + reg)); in vtd_write_reg32()
46 uintptr_t base_address = DEVICE_MMIO_GET(dev); in vtd_read_reg32() local
48 return sys_read32(base_address + reg); in vtd_read_reg32()
54 uintptr_t base_address = DEVICE_MMIO_GET(dev); in vtd_write_reg64() local
56 sys_write64(value, (base_address + reg)); in vtd_write_reg64()
61 uintptr_t base_address = DEVICE_MMIO_GET(dev); in vtd_read_reg64() local
63 return sys_read64(base_address + reg); in vtd_read_reg64()
69 uintptr_t base_address = DEVICE_MMIO_GET(dev); in vtd_send_cmd() local
77 while (!sys_test_bit((base_address + VTD_GSTS_REG), in vtd_send_cmd()
/drivers/memc/
A Dmemc_max32_hpb.c39 .base_addr = DT_PROP(n, base_address), \

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