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Searched refs:clock_ctrl (Results 1 – 5 of 5) sorted by relevance

/drivers/sdhc/
A Dintel_emmc_host.c187 regs->clock_ctrl &= ~EMMC_HOST_INTERNAL_CLOCK_EN; in emmc_disable_clock()
188 regs->clock_ctrl &= ~EMMC_HOST_SD_CLOCK_EN; in emmc_disable_clock()
190 while ((regs->clock_ctrl & EMMC_HOST_SD_CLOCK_EN) != 0) { in emmc_disable_clock()
201 regs->clock_ctrl |= EMMC_HOST_INTERNAL_CLOCK_EN; in emmc_enable_clock()
203 while ((regs->clock_ctrl & EMMC_HOST_INTERNAL_CLOCK_STABLE) == 0) { in emmc_enable_clock()
208 regs->clock_ctrl |= EMMC_HOST_SD_CLOCK_EN; in emmc_enable_clock()
209 while ((regs->clock_ctrl & EMMC_HOST_SD_CLOCK_EN) == 0) { in emmc_enable_clock()
262 SET_BITS(regs->clock_ctrl, EMMC_HOST_CLK_SDCLCK_FREQ_SEL_LOC, in emmc_clock_set()
264 SET_BITS(regs->clock_ctrl, EMMC_HOST_CLK_SDCLCK_FREQ_SEL_UPPER_LOC, in emmc_clock_set()
A Dxlnx_sdhc.h221 volatile uint16_t clock_ctrl; /**< Clock Control */ member
A Dxlnx_sdhc.c716 reg->clock_ctrl = 0; in xlnx_sdhc_set_clock()
738 reg->clock_ctrl = value; in xlnx_sdhc_set_clock()
739 ret = xlnx_sdhc_waitb_events((void *)&reg->clock_ctrl, 150, in xlnx_sdhc_set_clock()
746 reg->clock_ctrl |= XLNX_SDHC_CC_SD_CLK_EN_MASK; in xlnx_sdhc_set_clock()
A Dintel_emmc_host.h206 volatile uint16_t clock_ctrl; /**< Clock Control */ member
/drivers/serial/
A Duart_bflb.c80 const struct device *clock_ctrl = DEVICE_DT_GET_ANY(bflb_clock_controller); in uart_bflb_get_clock() local
85 clock_control_get_rate(clock_ctrl, (void *)BFLB_CLKID_CLK_ROOT, &uclk); in uart_bflb_get_clock()
89 clock_control_get_rate(clock_ctrl, (void *)BFLB_CLKID_CLK_BCLK, &uclk); in uart_bflb_get_clock()

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