Searched refs:clock_divider (Results 1 – 19 of 19) sorted by relevance
| /drivers/mdio/ |
| A D | mdio_xilinx_axienet.c | 45 uint16_t clock_divider; member
100 data->clock_divider); in enable_mdio_bus()
136 uint16_t clock_divider, clock_divider_full; in mdio_xilinx_axienet_bus_enable() local
146 clock_divider = clock_divider_full & XILINX_AXIENET_MDIO_SETUP_REG_MDIO_CLOCK_DIVIDER_MASK; in mdio_xilinx_axienet_bus_enable()
148 if (clock_divider != clock_divider_full) { in mdio_xilinx_axienet_bus_enable()
151 clock_divider = XILINX_AXIENET_MDIO_SETUP_REG_MDIO_CLOCK_DIVIDER_MASK; in mdio_xilinx_axienet_bus_enable()
154 data->clock_divider = clock_divider; in mdio_xilinx_axienet_bus_enable()
157 config->clock_frequency_hz, clock_divider); in mdio_xilinx_axienet_bus_enable()
160 clock_divider); in mdio_xilinx_axienet_bus_enable()
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| /drivers/can/ |
| A D | can_stm32h7_fdcan.c | 40 uint8_t clock_divider; member
170 if (stm32h7_cfg->clock_divider != 0U) { in can_stm32h7_clock_enable()
174 FIELD_PREP(FDCANCCU_CCFG_CDIV, stm32h7_cfg->clock_divider >> 1U); in can_stm32h7_clock_enable()
279 .clock_divider = DT_INST_PROP_OR(n, clk_divider, 0) \
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| A D | can_stm32_fdcan.c | 175 uint8_t clock_divider; member
466 if (stm32fd_cfg->clock_divider != 0) { in can_stm32fd_clock_enable()
468 FDCAN_CONFIG->CKDIV = stm32fd_cfg->clock_divider >> 1; in can_stm32fd_clock_enable()
610 .clock_divider = DT_INST_PROP_OR(inst, clk_divider, 0) \
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| A D | can_numaker.c | 297 .clk_div = DT_INST_CLOCKS_CELL(inst, clock_divider), \
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| /drivers/adc/ |
| A D | adc_max32.c | 30 int clock_divider; member
249 .clkdiv = config->clock_divider, in adc_max32_init()
321 .clock_divider = DT_INST_PROP_OR(_num, clock_divider, 1), \
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| A D | adc_numaker.c | 388 .clk_div = DT_INST_CLOCKS_CELL(inst, clock_divider), \
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| /drivers/misc/nxp_s32_emios/ |
| A D | nxp_s32_emios.c | 53 BUILD_ASSERT(IN_RANGE(DT_INST_PROP(n, clock_divider), \
58 .clkDivVal = DT_INST_PROP(n, clock_divider) - 1U, \
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| /drivers/clock_control/ |
| A D | clock_control_ifx_cat1_fixed_factor_clock.c | 55 .divider = DT_INST_PROP_OR(idx, clock_divider, 1u), \
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| /drivers/misc/ethos_u/ |
| A D | ethos_u_numaker.c | 96 .pcc.clk_div = DT_INST_CLOCKS_CELL(inst, clock_divider), \
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| /drivers/sdhc/ |
| A D | intel_emmc_host.c | 220 uint32_t clock_divider; in emmc_clock_set() local
258 clock_divider = (int)(base_freq / (freq * 2)); in emmc_clock_set()
260 LOG_DBG("Clock divider for MMC Clk: %d Hz is %d", speed, clock_divider); in emmc_clock_set()
263 EMMC_HOST_CLK_SDCLCK_FREQ_SEL_MASK, clock_divider); in emmc_clock_set()
265 EMMC_HOST_CLK_SDCLCK_FREQ_SEL_UPPER_MASK, clock_divider >> 8); in emmc_clock_set()
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| /drivers/watchdog/ |
| A D | wdt_wwdt_numaker.c | 300 .clk_div = DT_INST_CLOCKS_CELL(0, clock_divider),
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| /drivers/spi/ |
| A D | spi_numaker.c | 362 .clk_div = DT_INST_CLOCKS_CELL(inst, clock_divider), \
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| /drivers/serial/ |
| A D | uart_numaker.c | 443 .clk_div = DT_INST_CLOCKS_CELL(inst, clock_divider), \
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| /drivers/pwm/ |
| A D | pwm_numaker.c | 592 .clk_div = DT_INST_CLOCKS_CELL(inst, clock_divider), \
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| /drivers/ethernet/ |
| A D | eth_numaker.c | 789 .clk_div = DT_INST_CLOCKS_CELL(0, clock_divider),
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| /drivers/i2c/ |
| A D | i2c_numaker.c | 768 .clk_div = DT_INST_CLOCKS_CELL(inst, clock_divider), \
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| /drivers/usb/udc/ |
| A D | udc_numaker.c | 1797 .clk_div = DT_INST_CLOCKS_CELL(inst, clock_divider), \
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| /drivers/usb/device/ |
| A D | usb_dc_numaker.c | 1982 .clk_div = DT_INST_CLOCKS_CELL(inst, clock_divider), \
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| /drivers/usb_c/tcpc/ |
| A D | ucpd_numaker.c | 2357 .pcc.clk_div = DT_INST_CLOCKS_CELL_BY_NAME(inst, name, clock_divider), \
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