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Searched refs:ctrl (Results 1 – 25 of 76) sorted by relevance

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/drivers/video/
A Dvideo_ctrls.c153 ctrl->menu = NULL; in video_init_ctrl()
154 ctrl->vdev = vdev; in video_init_ctrl()
155 ctrl->id = id; in video_init_ctrl()
156 ctrl->type = type; in video_init_ctrl()
195 ctrl, dev, id, in video_init_menu_ctrl()
217 ctrl, dev, id, in video_init_int_menu_ctrl()
316 ctrl->cluster ? ctrl->cluster->id : ctrl->id); in video_get_ctrl()
384 if (ctrl == ctrl->cluster && ctrl->is_auto && ctrl->has_volatiles && in video_set_ctrl()
393 ->get_volatile_ctrl(ctrl->vdev->dev, ctrl->id); in video_set_ctrl()
403 ctrl->cluster ? ctrl->cluster->id : ctrl->id); in video_set_ctrl()
[all …]
A Dvideo_ctrls.h66 int video_init_ctrl(struct video_ctrl *ctrl, const struct device *dev, uint32_t id,
69 int video_init_menu_ctrl(struct video_ctrl *ctrl, const struct device *dev, uint32_t id,
72 int video_init_int_menu_ctrl(struct video_ctrl *ctrl, const struct device *dev, uint32_t id,
/drivers/i2c/
A Di2c_mchp_mss.c107 ctrl &= ~CTRL_ENS1; in mss_i2c_reset()
115 ctrl |= CTRL_ENS1; in mss_i2c_reset()
124 ctrl &= ~CLK_MASK; in mss_i2c_configure()
224 ctrl |= CTRL_STA; in mss_i2c_transfer()
287 uint8_t ctrl) in mss_i2c_set_ctrl_aa() argument
290 return ctrl; in mss_i2c_set_ctrl_aa()
375 ctrl = mss_i2c_set_ctrl_aa(data, msg_curr, ctrl); in mss_i2c_irq_handler()
377 ctrl |= CTRL_AA; in mss_i2c_irq_handler()
390 ctrl = mss_i2c_set_ctrl_aa(data, msg_curr, ctrl); in mss_i2c_irq_handler()
398 ctrl |= CTRL_STO; in mss_i2c_irq_handler()
[all …]
/drivers/counter/
A Dcounter_neorv32_gptmr.c62 uint32_t ctrl; in neorv32_gptmr_start() local
67 ctrl |= NEORV32_GPTMR_CTRL_EN; in neorv32_gptmr_start()
79 uint32_t ctrl; in neorv32_gptmr_stop() local
84 ctrl &= ~NEORV32_GPTMR_CTRL_EN; in neorv32_gptmr_stop()
105 uint32_t ctrl; in neorv32_gptmr_set_top_value() local
127 if ((ctrl & NEORV32_GPTMR_CTRL_EN) != 0U) { in neorv32_gptmr_set_top_value()
134 ctrl & ~NEORV32_GPTMR_CTRL_EN); in neorv32_gptmr_set_top_value()
155 uint32_t ctrl; in neorv32_gptmr_get_pending_int() local
189 uint32_t ctrl; in neorv32_gptmr_isr() local
194 ctrl |= NEORV32_GPTMR_CTRL_IRQ_CLR; in neorv32_gptmr_isr()
[all …]
A Dcounter_realtek_rts5912.c56 if (counter->ctrl & TIMER32_CTRL_EN) { in counter_rts5912_start()
60 counter->ctrl |= (TIMER32_CTRL_EN); in counter_rts5912_start()
72 if (!(counter->ctrl & TIMER32_CTRL_EN)) { in counter_rts5912_stop()
77 counter->ctrl = TIMER32_CTRL_INTEN_DIS; in counter_rts5912_stop()
128 counter->ctrl &= ~TIMER32_CTRL_EN; in counter_rts5912_set_alarm()
145 counter->ctrl |= TIMER32_CTRL_EN; in counter_rts5912_set_alarm()
163 counter->ctrl = 0; in counter_rts5912_cancel_alarm()
206 counter->ctrl &= ~TIMER32_CTRL_EN; in counter_rts5912_set_top_value()
227 counter->ctrl |= TIMER32_CTRL_EN; in counter_rts5912_set_top_value()
244 counter->ctrl &= ~TIMER32_CTRL_EN; in counter_rts5912_isr()
[all …]
A Dcounter_realtek_rts5912_slwtmr.c55 if (counter->ctrl & SLWTMR_CTRL_EN) { in counter_rts5912_start()
59 counter->ctrl |= SLWTMR_CTRL_EN; in counter_rts5912_start()
77 counter->ctrl = 0; in counter_rts5912_stop()
128 counter->ctrl = 0; in counter_rts5912_set_alarm()
137 counter->ctrl |= SLWTMR_CTRL_INTEN_EN; in counter_rts5912_set_alarm()
141 counter->ctrl |= SLWTMR_CTRL_EN; in counter_rts5912_set_alarm()
157 counter->ctrl = 0; in counter_rts5912_cancel_alarm()
199 counter->ctrl = 0; in counter_rts5912_set_top_value()
220 counter->ctrl |= SLWTMR_CTRL_EN; in counter_rts5912_set_top_value()
232 counter->ctrl &= ~SLWTMR_CTRL_EN; in counter_rts5912_isr()
[all …]
/drivers/timer/
A Dleon_gptimer.c27 uint32_t ctrl; member
72 uint32_t ctrl; in timer_isr() local
74 ctrl = tmr->ctrl; in timer_isr()
75 if ((ctrl & GPTIMER_CTRL_IP) == 0) { in timer_isr()
80 tmr->ctrl = GPTIMER_CTRL_IE | GPTIMER_CTRL_RS | in timer_isr()
103 tmr->ctrl = GPTIMER_CTRL_LD | GPTIMER_CTRL_RS | GPTIMER_CTRL_EN; in init_downcounter()
115 tmr->ctrl = GPTIMER_CTRL_IP; in sys_clock_driver_init()
116 if ((tmr->ctrl & GPTIMER_CTRL_IP) == 0) { in sys_clock_driver_init()
124 tmr->ctrl = GPTIMER_CTRL_IE | GPTIMER_CTRL_LD | GPTIMER_CTRL_RS | in sys_clock_driver_init()
A Dsam0_rtc_timer.c284 uint16_t ctrl = RTC_MODE0_CTRL_MODE(0) | RTC_MODE0_CTRL_PRESCALER(0); in sys_clock_driver_init() local
286 uint16_t ctrl = RTC_MODE0_CTRLA_MODE(0) | RTC_MODE0_CTRLA_PRESCALER(0); in sys_clock_driver_init() local
290 ctrl |= RTC_MODE0_CTRLA_COUNTSYNC; in sys_clock_driver_init()
295 ctrl |= RTC_MODE0_CTRL_MATCHCLR; in sys_clock_driver_init()
297 ctrl |= RTC_MODE0_CTRLA_MATCHCLR; in sys_clock_driver_init()
302 RTC0->CTRL.reg = ctrl; in sys_clock_driver_init()
304 RTC0->CTRLA.reg = ctrl; in sys_clock_driver_init()
/drivers/cache/
A Dcache_aspeed.c135 uint32_t ctrl; in cache_data_invd_all() local
138 syscon_read_reg(dev, CACHE_FUNC_CTRL_REG, &ctrl); in cache_data_invd_all()
145 ctrl &= ~DCACHE_CLEAN; in cache_data_invd_all()
146 syscon_write_reg(dev, CACHE_FUNC_CTRL_REG, ctrl); in cache_data_invd_all()
149 ctrl |= DCACHE_CLEAN; in cache_data_invd_all()
150 syscon_write_reg(dev, CACHE_FUNC_CTRL_REG, ctrl); in cache_data_invd_all()
197 uint32_t ctrl; in cache_instr_invd_all() local
207 ctrl &= ~ICACHE_CLEAN; in cache_instr_invd_all()
210 ctrl |= ICACHE_CLEAN; in cache_instr_invd_all()
312 uint32_t ctrl; in cache_data_line_size_get() local
[all …]
/drivers/serial/
A Duart_apbuart.c239 uint32_t ctrl = 0; in apbuart_configure() local
275 ctrl = regs->ctrl; in apbuart_configure()
277 regs->ctrl = ctrl | newctrl; in apbuart_configure()
286 const uint32_t ctrl = regs->ctrl; in apbuart_config_get() local
289 if (ctrl & APBUART_CTRL_PE) { in apbuart_config_get()
290 if (ctrl & APBUART_CTRL_PS) { in apbuart_config_get()
298 if (ctrl & APBUART_CTRL_FL) { in apbuart_config_get()
367 regs->ctrl |= APBUART_CTRL_TI; in apbuart_irq_tx_enable()
442 uint32_t ctrl = regs->ctrl; in apbuart_irq_is_pending() local
494 uint32_t ctrl; in apbuart_init() local
[all …]
A Duart_neorv32.c102 uint32_t ctrl; in neorv32_uart_poll_in() local
104 ctrl = neorv32_uart_read_ctrl(dev); in neorv32_uart_poll_in()
130 uint32_t ctrl; in neorv32_uart_configure() local
198 ctrl |= NEORV32_UART_CTRL_EN; in neorv32_uart_configure()
270 uint32_t ctrl; in neorv32_uart_irq_tx_enable() local
285 uint32_t ctrl; in neorv32_uart_irq_tx_disable() local
311 uint32_t ctrl; in neorv32_uart_irq_rx_enable() local
326 uint32_t ctrl; in neorv32_uart_irq_rx_disable() local
431 uint32_t ctrl; in neorv32_uart_pm_action() local
438 ctrl &= ~(NEORV32_UART_CTRL_EN); in neorv32_uart_pm_action()
[all …]
/drivers/ethernet/
A Deth_renesas_ra.c59 ether_instance_ctrl_t ctrl; member
163 ether_init_buffers(&ctx->ctrl); in renesas_ra_eth_buffer_init()
173 p_reg_etherc = (R_ETHERC0_Type *)ctx->ctrl.p_reg_etherc; in phy_link_state_changed()
179 ctx->ctrl.link_change = ETHER_LINK_CHANGE_LINK_UP; in phy_link_state_changed()
188 ether_configure_mac(&ctx->ctrl, ctx->ctrl.p_ether_cfg->p_mac_address, 0); in phy_link_state_changed()
219 ether_do_link(&ctx->ctrl, 0); in phy_link_state_changed()
220 ctx->ctrl.link_change = ETHER_LINK_CHANGE_LINK_UP; in phy_link_state_changed()
226 ctx->ctrl.link_change = ETHER_LINK_CHANGE_LINK_DOWN; in phy_link_state_changed()
250 err = R_ETHER_Open(&ctx->ctrl, cfg->p_cfg); in renesas_ra_eth_initialize()
285 err = R_ETHER_Write(&ctx->ctrl, tx_buf, len); in renesas_ra_eth_tx()
[all …]
/drivers/pcie/host/
A Dptm.c28 union ptm_ctrl_reg ctrl; in pcie_ptm_root_setup() local
36 ctrl.ptm_enable = 1; in pcie_ptm_root_setup()
37 ctrl.root_select = 1; in pcie_ptm_root_setup()
39 pcie_conf_write(config->pcie->bdf, base + PTM_CTRL_REG_OFFSET, ctrl.raw); in pcie_ptm_root_setup()
76 union ptm_ctrl_reg ctrl; in DT_INST_FOREACH_STATUS_OKAY() local
90 ctrl.ptm_enable = 1; in DT_INST_FOREACH_STATUS_OKAY()
92 pcie_conf_write(bdf, base + PTM_CTRL_REG_OFFSET, ctrl.raw); in DT_INST_FOREACH_STATUS_OKAY()
/drivers/entropy/
A Dentropy_neorv32_trng.c46 static inline void neorv32_trng_write_ctrl(const struct device *dev, uint32_t ctrl) in neorv32_trng_write_ctrl() argument
50 sys_write32(ctrl, config->base + NEORV32_TRNG_CTRL); in neorv32_trng_write_ctrl()
62 uint32_t ctrl; in neorv32_trng_get_entropy() local
65 ctrl = neorv32_trng_read_ctrl(dev); in neorv32_trng_get_entropy()
67 if ((ctrl & NEORV32_TRNG_CTRL_AVAIL) != 0) { in neorv32_trng_get_entropy()
79 uint32_t ctrl; in neorv32_trng_get_entropy_isr() local
83 ctrl = neorv32_trng_read_ctrl(dev); in neorv32_trng_get_entropy_isr()
84 if ((ctrl & NEORV32_TRNG_CTRL_AVAIL) != 0) { in neorv32_trng_get_entropy_isr()
/drivers/rtc/
A Drtc_ds3231.c103 if (ctrl->en_alarm_1) { in rtc_ds3231_ctrl_to_buf()
107 if (ctrl->en_alarm_2) { in rtc_ds3231_ctrl_to_buf()
111 switch (ctrl->sqw_freq) { in rtc_ds3231_ctrl_to_buf()
125 if (ctrl->intctrl) { in rtc_ds3231_ctrl_to_buf()
131 if (ctrl->conv) { in rtc_ds3231_ctrl_to_buf()
164 if (ctrl->a1f) { in rtc_ds3231_ctrl_sts_to_buf()
167 if (ctrl->a2f) { in rtc_ds3231_ctrl_sts_to_buf()
170 if (ctrl->osf) { in rtc_ds3231_ctrl_sts_to_buf()
173 if (ctrl->en_32khz) { in rtc_ds3231_ctrl_sts_to_buf()
176 if (ctrl->bsy) { in rtc_ds3231_ctrl_sts_to_buf()
[all …]
/drivers/gpio/
A Dgpio_shell.c175 for (i = 0; i < ctrl->ngpios && i < ctrl->line_names_len; i++) { in get_gpio_pin()
178 if ((BIT64(i) & ctrl->reserved_mask) != 0) { in get_gpio_pin()
200 const struct gpio_ctrl *ctrl; in get_sh_gpio() local
204 ctrl = get_gpio_ctrl(argv[ARGV_DEV]); in get_sh_gpio()
205 if (ctrl == NULL) { in get_sh_gpio()
209 gpio->dev = ctrl->dev; in get_sh_gpio()
531 for (pin = 0; pin < ctrl->ngpios; pin++) { in print_gpio_ctrl_info()
533 if (pin < ctrl->line_names_len) { in print_gpio_ctrl_info()
534 line_name = ctrl->line_names[pin]; in print_gpio_ctrl_info()
637 if (ctrl == NULL) { in cmd_gpio_info()
[all …]
A Dgpio_nxp_s32.c47 const struct device *ctrl; member
269 eirq_nxp_s32_disable_interrupt(irq_cfg->ctrl, irq_line); in nxp_s32_gpio_config_eirq()
270 eirq_nxp_s32_unset_callback(irq_cfg->ctrl, irq_line); in nxp_s32_gpio_config_eirq()
275 if (eirq_nxp_s32_set_callback(irq_cfg->ctrl, irq_line, pin, in nxp_s32_gpio_config_eirq()
280 eirq_nxp_s32_enable_interrupt(irq_cfg->ctrl, irq_line, eirq_trigger); in nxp_s32_gpio_config_eirq()
337 wkpu_nxp_s32_disable_interrupt(irq_cfg->ctrl, irq_line); in nxp_s32_gpio_config_wkpu()
338 wkpu_nxp_s32_unset_callback(irq_cfg->ctrl, irq_line); in nxp_s32_gpio_config_wkpu()
343 if (wkpu_nxp_s32_set_callback(irq_cfg->ctrl, irq_line, pin, in nxp_s32_gpio_config_wkpu()
348 wkpu_nxp_s32_enable_interrupt(irq_cfg->ctrl, irq_line, wkpu_trigger); in nxp_s32_gpio_config_wkpu()
528 .ctrl = DEVICE_DT_GET(GPIO_NXP_S32_EIRQ_NODE(n)), \
[all …]
/drivers/spi/
A Dspi_grlib_spimctrl.c19 uint32_t ctrl; member
120 regs->ctrl |= (CTRL_USRC | CTRL_IEN); in transceive()
121 regs->ctrl &= ~CTRL_CSN; in transceive()
134 regs->ctrl |= CTRL_CSN; in transceive()
135 regs->ctrl &= ~CTRL_USRC; in transceive()
180 regs->ctrl &= ~CTRL_IEN; in spim_isr()
198 regs->ctrl = CTRL_CSN; in init()
A Dspi_mchp_mss_qspi.c176 uint32_t count, ctrl, wdata; in mss_qspi_transmit_x32() local
179 ctrl |= MSS_QSPI_CONTROL_FLAGSX4; in mss_qspi_transmit_x32()
198 uint32_t count, ctrl, temp; in mss_qspi_receive_x32() local
201 ctrl |= MSS_QSPI_CONTROL_FLAGSX4; in mss_qspi_receive_x32()
394 ctrl |= MSS_QSPI_CONTROL_CLKIDLE; in mss_qspi_hw_mode_set()
397 ctrl &= ~MSS_QSPI_CONTROL_CLKIDLE; in mss_qspi_hw_mode_set()
404 ctrl &= ~(MSS_QSPI_CONTROL_MODE0); in mss_qspi_hw_mode_set()
405 ctrl |= (MSS_QSPI_CONTROL_MODE_EXQUAD); in mss_qspi_hw_mode_set()
408 ctrl &= ~(MSS_QSPI_CONTROL_MODE0); in mss_qspi_hw_mode_set()
409 ctrl |= (MSS_QSPI_CONTROL_MODE_EXDUAL); in mss_qspi_hw_mode_set()
[all …]
/drivers/watchdog/
A Dwdt_rpi_pico.c52 hw_clear_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); in wdt_rpi_pico_setup()
64 hw_clear_bits(&watchdog_hw->ctrl, in wdt_rpi_pico_setup()
68 hw_set_bits(&watchdog_hw->ctrl, in wdt_rpi_pico_setup()
83 hw_set_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); in wdt_rpi_pico_setup()
102 ticks_hw->ticks[TICK_WATCHDOG].ctrl = TICKS_WATCHDOG_CTRL_ENABLE_BITS; in wdt_rpi_pico_setup()
116 hw_clear_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); in wdt_rpi_pico_disable()
/drivers/input/
A Dinput_realtek_rts5912_kbd.c83 inst->ctrl |= KBM_CTRL_KSIINTSTS_Msk; in rts5912_intc_isr_clear()
149 inst->ctrl |= KBM_CTRL_KSI8EN_Msk; in rts5912_kbd_init()
154 inst->ctrl |= KBM_CTRL_KSI9EN_Msk; in rts5912_kbd_init()
159 inst->ctrl |= KBM_CTRL_KSO18EN_Msk; in rts5912_kbd_init()
164 inst->ctrl |= KBM_CTRL_KSO19EN_Msk; in rts5912_kbd_init()
168 inst->ctrl |= KBM_CTRL_KSOTYPE_Msk; in rts5912_kbd_init()
/drivers/mspi/
A Dmspi_dw.c461 struct xip_ctrl *ctrl) in apply_xip_io_mode() argument
476 ctrl->read |= FIELD_PREP(XIP_CTRL_FRF_MASK, in apply_xip_io_mode()
484 ctrl->read |= FIELD_PREP(XIP_CTRL_FRF_MASK, in apply_xip_io_mode()
492 ctrl->read |= FIELD_PREP(XIP_CTRL_FRF_MASK, in apply_xip_io_mode()
538 struct xip_ctrl *ctrl) in apply_xip_cmd_length() argument
550 ctrl->read |= XIP_CTRL_INST_EN_BIT in apply_xip_cmd_length()
557 ctrl->read |= XIP_CTRL_INST_EN_BIT in apply_xip_cmd_length()
572 struct xip_ctrl *ctrl) in apply_xip_addr_length() argument
1230 struct xip_ctrl ctrl = {0}; in _api_xip_config() local
1270 write_xip_ctrl(dev, ctrl.read); in _api_xip_config()
[all …]
/drivers/clock_control/
A Dclock_control_it51xxx.c69 sys_write8(sys_read8(config->ecpm_base + clk_cfg->ctrl) & ~(clk_cfg->bits), in clock_control_it51xxx_on()
70 config->ecpm_base + clk_cfg->ctrl); in clock_control_it51xxx_on()
83 tmp_mask = (clk_cfg->ctrl == IT51XXX_ECPM_CGCTRL3R_OFF) ? 0x40 : 0x00; in clock_control_it51xxx_off()
84 sys_write8(sys_read8(config->ecpm_base + clk_cfg->ctrl) | clk_cfg->bits | tmp_mask, in clock_control_it51xxx_off()
85 config->ecpm_base + clk_cfg->ctrl); in clock_control_it51xxx_off()
/drivers/adc/
A Dadc_realtek_rts5912.c52 regs->ctrl |= ADC_CTRL_SGLDNINTEN; in adc_context_start_sampling()
53 regs->ctrl |= ADC_CTRL_START; in adc_context_start_sampling()
125 regs->ctrl |= ADC_CTRL_EN; in adc_rts5912_enable()
134 regs->ctrl &= ~ADC_CTRL_EN; in adc_rts5912_enable()
222 regs->ctrl &= ~(ADC_CTRL_SGLDNINTEN); in adc_rts5912_single_isr()
227 regs->ctrl &= ~ADC_CTRL_EN; in adc_rts5912_single_isr()
261 regs->ctrl = ADC_CTRL_RST; in adc_rts5912_init()
/drivers/pinctrl/
A Dpinctrl_npcx.c164 const struct npcx_dev_ctl *ctrl = (const struct npcx_dev_ctl *)&pin->cfg.dev_ctl; in npcx_device_control_configure() local
167 SET_FIELD(NPCX_DEV_CTL(scfg_base, ctrl->offest), in npcx_device_control_configure()
168 FIELD(ctrl->field_offset, ctrl->field_size), in npcx_device_control_configure()
169 ctrl->field_value); in npcx_device_control_configure()

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