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Searched refs:devcfg (Results 1 – 11 of 11) sorted by relevance

/drivers/clock_control/
A Dclock_control_mchp_xec.c280 const struct xec_pcr_config * const devcfg = dev->config; in soc_clk32_init() local
433 const struct xec_pcr_config * const devcfg = dev->config; in disable_32k_crystal() local
507 pcr->CNT32K_PER_MIN = devcfg->period_min; in check_32k_crystal()
508 pcr->CNT32K_PER_MAX = devcfg->period_max; in check_32k_crystal()
509 pcr->CNT32K_DV_MAX = devcfg->max_dc_va; in check_32k_crystal()
510 pcr->CNT32K_VALID_MIN = devcfg->min_valid; in check_32k_crystal()
702 if (!devcfg->clkmon_bypass) { in soc_clk32_init()
726 if (devcfg->dis_internal_osc) { in soc_clk32_init()
734 if (devcfg->dis_internal_osc) { in soc_clk32_init()
1027 enum pll_clk32k_src pll_clk_src = devcfg->pll_src; in xec_clock_control_init()
[all …]
/drivers/serial/
A Duart_mchp_mec5.c150 struct mec_uart_regs *const regs = devcfg->regs; in config_mec5_uart()
162 mcfg = uart_mec5_fifo_config(mcfg, devcfg->flags); in config_mec5_uart()
166 extclk = devcfg->clock_freq; in config_mec5_uart()
252 struct mec_uart_regs *const regs = devcfg->regs; in uart_mec5_poll_in()
272 struct mec_uart_regs *const regs = devcfg->regs; in uart_mec5_poll_out()
288 struct mec_uart_regs *const regs = devcfg->regs; in irq_tx_enable()
301 struct mec_uart_regs *const regs = devcfg->regs; in irq_tx_disable()
313 struct mec_uart_regs *const regs = devcfg->regs; in irq_rx_enable()
325 struct mec_uart_regs *const regs = devcfg->regs; in irq_rx_disable()
337 struct mec_uart_regs *const regs = devcfg->regs; in uart_mec5_fifo_fill()
[all …]
/drivers/ps2/
A Dps2_mchp_xec.c235 struct ps2_regs * const regs = devcfg->regs; in ps2_xec_pm_action()
240 if (devcfg->wakeup_source) { in ps2_xec_pm_action()
244 if (devcfg->wakerx_gpio.port != NULL) { in ps2_xec_pm_action()
246 &devcfg->wakerx_gpio, in ps2_xec_pm_action()
253 ps2_xec_girq_dis(devcfg->girq_id_wk, devcfg->girq_bit_wk); in ps2_xec_pm_action()
254 ps2_xec_girq_clr(devcfg->girq_id_wk, devcfg->girq_bit_wk); in ps2_xec_pm_action()
261 if (devcfg->wakeup_source) { in ps2_xec_pm_action()
265 ps2_xec_girq_clr(devcfg->girq_id_wk, devcfg->girq_bit_wk); in ps2_xec_pm_action()
266 ps2_xec_girq_en(devcfg->girq_id_wk, devcfg->girq_bit_wk); in ps2_xec_pm_action()
267 if (devcfg->wakerx_gpio.port != NULL) { in ps2_xec_pm_action()
[all …]
/drivers/dma/
A Ddma_mchp_xec.c166 return &devcfg->irq_info_list[channel]; in xec_chan_irq_info()
339 struct dma_xec_regs * const regs = devcfg->regs; in dma_xec_configure()
456 struct dma_xec_regs * const regs = devcfg->regs; in dma_xec_reload()
459 if (channel >= (uint32_t)devcfg->dma_channels) { in dma_xec_reload()
499 struct dma_xec_regs * const regs = devcfg->regs; in dma_xec_start()
502 if (channel >= (uint32_t)devcfg->dma_channels) { in dma_xec_start()
532 struct dma_xec_regs * const regs = devcfg->regs; in dma_xec_stop()
637 if (!filter_param && devcfg->dma_channels) { in dma_xec_chan_filter()
638 filter = GENMASK(devcfg->dma_channels-1u, 0); in dma_xec_chan_filter()
758 z_mchp_xec_pcr_periph_sleep(devcfg->pcr_idx, devcfg->pcr_pos, 0); in dma_xec_init()
[all …]
/drivers/spi/
A Dspi_mchp_mec5_qspi.c98 const struct mec5_qspi_config *devcfg = dev->config; in get_cs_timing_from_dt() local
161 struct mec_qspi_regs *regs = devcfg->regs; in mec5_qspi_configure()
241 struct mec_qspi_regs *regs = devcfg->regs; in mec5_qspi_do_xfr()
277 mec_hal_qspi_force_stop(devcfg->regs); in mec5_qspi_do_xfr()
351 struct mec_qspi_regs *regs = devcfg->regs; in mec5_qspi_ctx_next()
378 txb = &devcfg->ovrc; in mec5_qspi_ctx_next()
402 struct mec_qspi_regs *regs = devcfg->regs; in mec5_qspi_isr()
437 struct mec_qspi_regs *regs = devcfg->regs; in mec5_qspi_init()
452 data->freq = devcfg->clock_freq; in mec5_qspi_init()
467 if ((devcfg->irq_config_func) != NULL) { in mec5_qspi_init()
[all …]
A Dspi_xec_qmspi_ldma.c444 const struct spi_qmspi_config *devcfg = dev->config; in qmspi_xfr_cm_init() local
446 struct qmspi_regs *regs = devcfg->regs; in qmspi_xfr_cm_init()
534 const struct spi_qmspi_config *devcfg = dev->config; in q_ldma_cfg() local
537 struct qmspi_regs *regs = devcfg->regs; in q_ldma_cfg()
616 const struct spi_qmspi_config *devcfg = dev->config; in qmspi_xfr_sync() local
619 struct qmspi_regs *regs = devcfg->regs; in qmspi_xfr_sync()
677 const struct spi_qmspi_config *devcfg = dev->config; in qmspi_xfr_start_async() local
679 struct qmspi_regs *regs = devcfg->regs; in qmspi_xfr_start_async()
895 const struct spi_qmspi_config *devcfg = dev->config; in qmspi_xec_pm_action() local
900 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_DEFAULT); in qmspi_xec_pm_action()
[all …]
/drivers/pwm/
A Dpwm_mchp_xec_bbled.c271 const struct pwm_bbled_xec_config *const devcfg = dev->config; in pwm_bbled_xec_pm_action() local
272 struct bbled_regs * const regs = devcfg->regs; in pwm_bbled_xec_pm_action()
282 if ((!devcfg->enable_low_power_32K) && in pwm_bbled_xec_pm_action()
289 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_DEFAULT); in pwm_bbled_xec_pm_action()
311 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_SLEEP); in pwm_bbled_xec_pm_action()
A Dpwm_mchp_xec.c380 const struct pwm_xec_config *const devcfg = dev->config; in pwm_xec_pm_action() local
381 struct pwm_regs * const regs = devcfg->regs; in pwm_xec_pm_action()
387 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_DEFAULT); in pwm_xec_pm_action()
408 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_SLEEP); in pwm_xec_pm_action()
/drivers/adc/
A Dadc_mchp_xec.c111 const struct adc_xec_config * const devcfg = adc_dev->config; in adc_context_start_sampling() local
112 struct adc_xec_regs *regs = devcfg->regs; in adc_context_start_sampling()
373 const struct adc_xec_config *const devcfg = dev->config; in adc_xec_pm_action() local
374 struct adc_xec_regs * const adc_regs = devcfg->regs; in adc_xec_pm_action()
379 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_DEFAULT); in adc_xec_pm_action()
389 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_SLEEP); in adc_xec_pm_action()
/drivers/eeprom/
A Deeprom_mchp_xec.c307 const struct eeprom_xec_config *const devcfg = dev->config; in eeprom_xec_pm_action() local
308 struct eeprom_xec_regs * const regs = devcfg->regs; in eeprom_xec_pm_action()
313 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_DEFAULT); in eeprom_xec_pm_action()
323 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_SLEEP); in eeprom_xec_pm_action()
/drivers/peci/
A Dpeci_mchp_xec.c447 const struct peci_xec_config *const devcfg = dev->config; in peci_xec_pm_action() local
448 struct peci_regs * const regs = devcfg->regs; in peci_xec_pm_action()
454 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_DEFAULT); in peci_xec_pm_action()
471 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_SLEEP); in peci_xec_pm_action()

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