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Searched refs:divisor (Results 1 – 20 of 20) sorted by relevance

/drivers/sensor/st/vl53l1x/
A Dvl53l1_platform_user_defines.h31 #define do_division_u(dividend, divisor) (dividend / divisor) argument
41 #define do_division_s(dividend, divisor) (dividend / divisor) argument
/drivers/watchdog/
A Dwdt_renesas_ra.c106 for (unsigned int divisor = WDT_CLOCK_DIVISION_1; divisor < ARRAY_SIZE(clock_div_lut); in wdt_renesas_ra_timeout_calculate() local
107 divisor++) { in wdt_renesas_ra_timeout_calculate()
111 (unsigned int)(1000.0F * clock_div_lut[divisor] * in wdt_renesas_ra_timeout_calculate()
119 best_divisor = divisor; in wdt_renesas_ra_timeout_calculate()
/drivers/serial/
A Duart_xlnx_ps.c235 uint32_t divisor, generator; in set_baudrate() local
244 for (divisor = 4; divisor < 255; divisor++) { in set_baudrate()
247 generator = clk_freq / (baud * (divisor + 1)); in set_baudrate()
251 tmpbaud = clk_freq / (generator * (divisor + 1)); in set_baudrate()
269 sys_write32(divisor, reg_base + XUARTPS_BAUDDIV_OFFSET); in set_baudrate()
A Duart_renesas_rza2m_scif.c181 int16_t divisor; /* Clock divisor */ member
240 ((ratio >= (uint32_t)(gs_scifa_async_baud[divisor_index].divisor * 256)) || in find_divisor_index()
247 (ratio >= (uint32_t)(gs_scifa_async_baud[divisor_index].divisor * 256))) { in find_divisor_index()
263 uint32_t divisor; in uart_rza2m_scif_set_baudrate() local
267 divisor = (uint32_t)gs_scifa_async_baud[divisor_index].divisor; in uart_rza2m_scif_set_baudrate()
269 brr = clk_freq / (divisor * baud_rate); in uart_rza2m_scif_set_baudrate()
276 brr = clk_freq / ((divisor * baud_rate) / 2); in uart_rza2m_scif_set_baudrate()
A Duart_sam.c107 uint32_t divisor; in uart_sam_baudrate_set() local
114 divisor = SOC_ATMEL_SAM_MCK_FREQ_HZ / 16U / baudrate; in uart_sam_baudrate_set()
116 if (divisor > 0xFFFF) { in uart_sam_baudrate_set()
120 uart->UART_BRGR = UART_BRGR_CD(divisor); in uart_sam_baudrate_set()
A Dusart_sam.c106 uint32_t divisor; in usart_sam_baudrate_set() local
127 divisor = rate / 16U / baudrate; in usart_sam_baudrate_set()
129 if (divisor > 0xFFFF) { in usart_sam_baudrate_set()
133 usart->US_BRGR = US_BRGR_CD(divisor); in usart_sam_baudrate_set()
A Duart_ns16550.c505 uint32_t divisor = 0; local
510 divisor = IT8XXX2_230400_DIVISOR;
512 divisor = IT8XXX2_460800_DIVISOR;
522 divisor = get_uart_baudrate_divisor(dev, baud_rate, pclk);
527 return divisor;
547 uint32_t divisor; /* baud rate divisor */ local
552 divisor = get_ite_uart_baudrate_divisor(dev, baud_rate, pclk);
554 divisor = get_uart_baudrate_divisor(dev, baud_rate, pclk);
559 ns16550_outbyte(dev_cfg, BRDL(dev), (unsigned char)(divisor & 0xff));
560 ns16550_outbyte(dev_cfg, BRDH(dev), (unsigned char)((divisor >> 8) & 0xff));
A Duart_mchp_xec.c293 uint32_t divisor; /* baud rate divisor */ in set_baud_rate() local
301 divisor = ((dev_cfg->sys_clk_freq + (baud_rate << 3)) in set_baud_rate()
307 regs->RTXB = (unsigned char)(divisor & 0xff); in set_baud_rate()
309 regs->IER = (unsigned char)((divisor >> 8) & 0x7f); in set_baud_rate()
/drivers/sensor/bosch/bmp180/
A Dbmp180.c263 int32_t divisor; in bmp180_compensate_temp() local
269 divisor = partial_data1 + cal->md; in bmp180_compensate_temp()
270 __ASSERT(divisor != 0, "divisor is zero: partial_data1=%d, md=%d", partial_data1, cal->md); in bmp180_compensate_temp()
272 partial_data2 = cal->mc * 0x800 / divisor; in bmp180_compensate_temp()
/drivers/sdhc/
A DKconfig.sam_hsmci35 is the divisor value. Valid values are 0 to 7.
A Drcar_mmc.c1093 uint32_t divisor; in rcar_mmc_set_clk_rate() local
1114 divisor = DIV_ROUND_UP(cfg->max_frequency, ios->clock); in rcar_mmc_set_clk_rate()
1117 if (data->ddr_mode && (divisor == 1)) { in rcar_mmc_set_clk_rate()
1118 divisor = 2; in rcar_mmc_set_clk_rate()
1121 divisor = round_up_next_pwr_of_2(divisor); in rcar_mmc_set_clk_rate()
1122 if (divisor == 1) { in rcar_mmc_set_clk_rate()
1123 divisor = RCAR_MMC_CLKCTL_RCAR_DIV1; in rcar_mmc_set_clk_rate()
1125 divisor >>= 2; in rcar_mmc_set_clk_rate()
1139 (mmc_clk_ctl & RCAR_MMC_CLKCTL_DIV_MASK) == divisor) { in rcar_mmc_set_clk_rate()
1155 mmc_clk_ctl |= divisor; in rcar_mmc_set_clk_rate()
A Dxlnx_sdhc.c611 uint16_t divisor = 0U, clockval = 0U; in xlnx_sdhc_cal_clock() local
614 divisor = 0U; in xlnx_sdhc_cal_clock()
618 divisor = divcnt >> XLNX_SDHC_CLOCK_CNT_SHIFT; in xlnx_sdhc_cal_clock()
624 clockval |= (divisor & XLNX_SDHC_CC_SDCLK_FREQ_SEL) << XLNX_SDHC_CC_DIV_SHIFT; in xlnx_sdhc_cal_clock()
625 clockval |= ((divisor >> XLNX_SDHC_CC_DIV_SHIFT) & XLNX_SDHC_CC_SDCLK_FREQ_SEL_EXT) << in xlnx_sdhc_cal_clock()
/drivers/mspi/
A DKconfig.dw15 int "Designware SSI TX Drive edge divisor"
/drivers/spi/
A Dspi_litex.c46 uint16_t divisor = DIV_ROUND_UP(sys_clock_hw_cycles_per_sec(), config->frequency); in spi_set_frequency() local
48 litex_write16(divisor, dev_config->clk_divider_addr); in spi_set_frequency()
A Dspi_it51xxx.c146 uint8_t divisor; in spi_it51xxx_set_freq() local
161 divisor = i; in spi_it51xxx_set_freq()
173 divisor = i; in spi_it51xxx_set_freq()
184 reg_val |= FIELD_PREP(SSCK_FREQ_MASK, divisor); in spi_it51xxx_set_freq()
A Dspi_litex_litespi.c68 uint32_t divisor = DIV_ROUND_UP(sys_clock_hw_cycles_per_sec(), (2 * config->frequency)) - 1; in spi_litex_set_frequency() local
70 litex_write32(divisor, dev_config->phy_clk_divisor_addr); in spi_litex_set_frequency()
/drivers/i2c/
A Di2c_renesas_ra_sci_b.c487 uint32_t divisor = 0; in calc_sci_b_iic_clock_setting() local
513 divisor = divisor_bitrate_multiple * bitrate; in calc_sci_b_iic_clock_setting()
518 brr = (uint32_t)ceil(((double)peripheral_clock) / divisor - 1); in calc_sci_b_iic_clock_setting()
536 temp_mddr = (uint32_t)floor(((double)divisor) * 256 * (temp_brr + 1) / in calc_sci_b_iic_clock_setting()
/drivers/i2s/
A Di2s_ll_stm32.c26 static unsigned int div_round_closest(uint32_t dividend, uint32_t divisor) in div_round_closest() argument
28 return (dividend + (divisor / 2U)) / divisor; in div_round_closest()
A Di2s_renesas_ra_ssie.c135 static ssi_clock_div_t get_ssi_clock_div_enum(uint32_t divisor) in get_ssi_clock_div_enum() argument
137 switch (divisor) { in get_ssi_clock_div_enum()
/drivers/timer/
A DKconfig.x8691 int "TSC to local APIC timer frequency divisor (M)"

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