Home
last modified time | relevance | path

Searched refs:fr (Results 1 – 8 of 8) sorted by relevance

/drivers/serial/
A Duart_stellaris.c42 uint32_t fr; member
182 while (config->uart->fr & UARTFR_BUSY) { in disable()
253 return (config->uart->fr & UARTFR_TXFE); in poll_tx_ready()
269 if (config->uart->fr & UARTFR_RXFE) { in uart_stellaris_poll_in()
318 while ((len - num_tx > 0) && ((config->uart->fr & UARTFR_TXFF) == 0U)) { in uart_stellaris_fifo_fill()
341 while ((size - num_rx > 0) && ((config->uart->fr & UARTFR_RXFE) == 0U)) { in uart_stellaris_fifo_read()
386 while (config->uart->fr & UARTFR_BUSY) { in uart_stellaris_irq_tx_enable()
A Duart_pl011.c187 return (get_uart(dev)->fr & PL011_FR_RXFE) == 0U; in pl011_is_readable()
206 while (get_uart(dev)->fr & PL011_FR_TXFF) { in pl011_poll_out()
358 while (!(get_uart(dev)->fr & PL011_FR_TXFF) && (len - num_tx > 0)) { in pl011_fifo_fill()
369 while ((len - num_rx > 0) && !(get_uart(dev)->fr & PL011_FR_RXFE)) { in pl011_fifo_read()
426 return ((get_uart(dev)->fr & PL011_FR_BUSY) == 0); in pl011_irq_tx_complete()
439 (get_uart(dev)->ris & PL011_RIS_TXRIS || get_uart(dev)->fr & PL011_FR_TXFE)); in pl011_irq_tx_ready()
461 (!(get_uart(dev)->fr & PL011_FR_RXFE))); in pl011_irq_rx_ready()
A Duart_pl011_registers.h24 uint32_t fr; /* flags register */ member
A Duart_pl011_ambiq.h134 while ((get_uart(dev)->fr & PL011_FR_BUSY) != 0) { in uart_ambiq_pm_action()
/drivers/input/
A DKconfig.vs1838b1 # Copyright (c) 2025 Bastien Jauny <bastien.jauny@smile.fr>
A DKconfig.chsc6x1 # Copyright (c) 2024 Nicolas Goualard <nicolas.goualard@sfr.fr>
/drivers/display/
A Ddisplay_ist3931.c31 uint16_t fr; /* frame_frequency_division */ member
88 uint8_t cmd_buf[3] = {IST3931_CMD_FRAME_CONTROL, config->fr & 0x00FF, config->fr >> 8}; in ist3931_set_fr()
275 .fr = DT_INST_PROP(inst, frame_control), \
/drivers/disk/nvme/
A Dnvme.h113 uint8_t fr[NVME_FIRMWARE_REVISION_LENGTH]; member

Completed in 21 milliseconds