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Searched refs:host_ctrl1 (Results 1 – 4 of 4) sorted by relevance

/drivers/sdhc/
A Dxlnx_sdhc.c765 reg->host_ctrl1 &= ~XLNX_SDHC_DAT_WIDTH8_MASK; in xlnx_sdhc_set_buswidth()
766 reg->host_ctrl1 &= ~XLNX_SDHC_DAT_WIDTH4_MASK; in xlnx_sdhc_set_buswidth()
770 reg->host_ctrl1 &= ~XLNX_SDHC_DAT_WIDTH8_MASK; in xlnx_sdhc_set_buswidth()
771 reg->host_ctrl1 |= XLNX_SDHC_DAT_WIDTH4_MASK; in xlnx_sdhc_set_buswidth()
775 reg->host_ctrl1 |= XLNX_SDHC_DAT_WIDTH8_MASK; in xlnx_sdhc_set_buswidth()
1032 reg->host_ctrl1 &= ~XLNX_SDHC_HS_SPEED_MODE_EN_MASK; in xlnx_sdhc_set_timing()
1037 reg->host_ctrl1 |= XLNX_SDHC_HS_SPEED_MODE_EN_MASK; in xlnx_sdhc_set_timing()
1190 reg->host_ctrl1 = XLNX_SDHC_ADMA2_64; in xlnx_sdhc_host_reset()
A Dxlnx_sdhc.h217 volatile uint8_t host_ctrl1; /**< Host Control 1 */ member
A Dintel_emmc_host.h202 volatile uint8_t host_ctrl1; /**< Host Control 1 */ member
A Dintel_emmc_host.c467 SET_BITS(regs->host_ctrl1, EMMC_HOST_CTRL1_DMA_SEL_LOC, in emmc_init_xfr()
470 SET_BITS(regs->host_ctrl1, EMMC_HOST_CTRL1_DMA_SEL_LOC, in emmc_init_xfr()
1044 SET_BITS(regs->host_ctrl1, EMMC_HOST_CTRL1_EXT_DAT_WIDTH_LOC, in emmc_set_io()
1048 SET_BITS(regs->host_ctrl1, EMMC_HOST_CTRL1_DAT_WIDTH_LOC, in emmc_set_io()

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