Searched refs:msix (Results 1 – 6 of 6) sorted by relevance
39 const struct nxp_s32_eth_msix *msix; in nxp_s32_eth_iface_init() local63 msix = &cfg->msix[i]; in nxp_s32_eth_iface_init()64 if (mbox_is_ready_dt(&msix->mbox_spec)) { in nxp_s32_eth_iface_init()65 if (mbox_set_enabled_dt(&msix->mbox_spec, true)) { in nxp_s32_eth_iface_init()67 msix->mbox_spec.channel_id); in nxp_s32_eth_iface_init()171 .msix = { \
37 const struct nxp_s32_eth_msix *msix = (const struct nxp_s32_eth_msix *)user_data; in nxp_s32_eth_msix_wrapper() local43 msix->handler(channel, NULL, 0); in nxp_s32_eth_msix_wrapper()56 const struct nxp_s32_eth_msix *msix; in nxp_s32_eth_initialize_common() local70 msix = &cfg->msix[i]; in nxp_s32_eth_initialize_common()71 if (mbox_is_ready_dt(&msix->mbox_spec)) { in nxp_s32_eth_initialize_common()72 err = mbox_register_callback_dt(&msix->mbox_spec, in nxp_s32_eth_initialize_common()74 (void *)msix); in nxp_s32_eth_initialize_common()77 msix->mbox_spec.channel_id); in nxp_s32_eth_initialize_common()
165 const struct nxp_s32_eth_msix *msix; in nxp_s32_eth_iface_init() local201 msix = &cfg->msix[i]; in nxp_s32_eth_iface_init()202 if (mbox_is_ready_dt(&msix->mbox_spec)) { in nxp_s32_eth_iface_init()203 if (mbox_set_enabled_dt(&msix->mbox_spec, true)) { in nxp_s32_eth_iface_init()205 msix->mbox_spec.channel_id); in nxp_s32_eth_iface_init()423 .msix = { \
117 struct nxp_s32_eth_msix msix[NETC_MSIX_EVENTS_COUNT]; member
275 uint8_t msix = info->id; in eth_intel_igc_queue_isr() local278 k_work_submit(&data->tx_work[msix]); in eth_intel_igc_queue_isr()279 k_work_schedule(&data->rx_work[msix], K_MSEC(0)); in eth_intel_igc_queue_isr()290 for (uint8_t msix = 0; msix < cfg->num_queues; msix++) { in eth_intel_igc_connect_queue_msix_vector() local293 info->id = msix; in eth_intel_igc_connect_queue_msix_vector()353 for (uint8_t msix = 0; msix < cfg->num_queues; msix++) { in eth_intel_igc_map_intr_to_vector() local354 reg_idx = msix >> 1; in eth_intel_igc_map_intr_to_vector()357 if (msix % 2) { in eth_intel_igc_map_intr_to_vector()366 config |= (msix | INTEL_IGC_IVAR_INT_VALID_BIT); in eth_intel_igc_map_intr_to_vector()434 for (uint8_t msix = 0; msix < cfg->num_queues; msix++) { in eth_intel_igc_intr_enable() local[all …]
113 bool msix) in set_msix() argument118 vectors[i].msix = msix; in set_msix()
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