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Searched refs:node_id (Results 1 – 25 of 113) sorted by relevance

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/drivers/gpio/
A Dgpio_hogs.c39 DT_PROP_OR(node_id, gpio_controller, 0)
42 #define GPIO_HOGS_NODE_IS_GPIO_HOG(node_id) \ argument
54 GPIO_HOG_DT_SPEC_GET_BY_IDX(node_id, idx)
57 #define GPIO_HOGS_INIT_GPIO_HOGS(node_id) \ argument
58 LISTIFY(DT_NUM_GPIO_HOGS(node_id), \
64 (GPIO_HOGS_INIT_GPIO_HOGS(node_id)), ())
67 #define GPIO_HOGS_INIT_GPIO_CTLR(node_id) \ argument
69 .port = DEVICE_DT_GET(node_id), \
71 DT_FOREACH_CHILD_STATUS_OKAY(node_id, \
82 (GPIO_HOGS_INIT_GPIO_CTLR(node_id)))
[all …]
/drivers/memc/
A Dmemc_stm32_nor_psram.c116 .NSBank = DT_REG_ADDR(node_id), \
117 .DataAddressMux = DT_PROP_BY_IDX(node_id, st_control, 0), \
118 .MemoryType = DT_PROP_BY_IDX(node_id, st_control, 1), \
119 .MemoryDataWidth = DT_PROP_BY_IDX(node_id, st_control, 2), \
120 .BurstAccessMode = DT_PROP_BY_IDX(node_id, st_control, 3), \
121 .WaitSignalPolarity = DT_PROP_BY_IDX(node_id, st_control, 4), \
122 .WaitSignalActive = DT_PROP_BY_IDX(node_id, st_control, 5), \
123 .WriteOperation = DT_PROP_BY_IDX(node_id, st_control, 6), \
124 .WaitSignal = DT_PROP_BY_IDX(node_id, st_control, 7), \
125 .ExtendedMode = DT_PROP_BY_IDX(node_id, st_control, 8), \
[all …]
A Dmemc_sam_smc.c64 #define SETUP_TIMING(node_id) \ argument
65 SMC_SETUP_NWE_SETUP(DT_PROP_BY_IDX(node_id, atmel_smc_setup_timing, 0)) \
69 #define PULSE_TIMING(node_id) \ argument
74 #define CYCLE_TIMING(node_id) \ argument
78 #define BANK_CONFIG(node_id) \ argument
80 .cs = DT_REG_ADDR(node_id), \
81 .mode = COND_CODE_1(DT_ENUM_IDX(node_id, atmel_smc_write_mode), \
83 | COND_CODE_1(DT_ENUM_IDX(node_id, atmel_smc_read_mode), \
85 .setup_timing = SETUP_TIMING(node_id), \
86 .pulse_timing = PULSE_TIMING(node_id), \
[all …]
A Dmemc_stm32_sdram.c93 .SDBank = DT_REG_ADDR(node_id), \
94 .ColumnBitsNumber = DT_PROP_BY_IDX(node_id, st_sdram_control, 0), \
95 .RowBitsNumber = DT_PROP_BY_IDX(node_id, st_sdram_control, 1), \
96 .MemoryDataWidth = DT_PROP_BY_IDX(node_id, st_sdram_control, 2), \
97 .InternalBankNumber = DT_PROP_BY_IDX(node_id, st_sdram_control, 3),\
98 .CASLatency = DT_PROP_BY_IDX(node_id, st_sdram_control, 4), \
100 .SDClockPeriod = DT_PROP_BY_IDX(node_id, st_sdram_control, 5), \
101 .ReadBurst = DT_PROP_BY_IDX(node_id, st_sdram_control, 6), \
102 .ReadPipeDelay = DT_PROP_BY_IDX(node_id, st_sdram_control, 7), \
105 .LoadToActiveDelay = DT_PROP_BY_IDX(node_id, st_sdram_timing, 0), \
[all …]
A Dmemc_nxp_s32_qspi.c163 #define QSPI_SECURE_ATTRIBUTE(node_id) \ argument
170 #define _QSPI_SFP_MDAD_CFG(node_id, n) \ argument
175 .Mask = DT_PROP(node_id, mask), \
176 .DomainId = DT_PROP(node_id, domain_id), \
188 #define QSPI_ACP_POLICY(node_id) \ argument
199 #define QSPI_EXCLUSIVE_ACCESS_LOCK(node_id) \ argument
204 #define _QSPI_SFP_FRAD_CFG(node_id, n) \ argument
206 .StartAddress = DT_REG_ADDR(node_id), \
207 .EndAddress = DT_REG_ADDR(node_id) + DT_REG_SIZE(node_id) - 1, \
209 .Md0Acp = QSPI_ACP_POLICY(node_id), \
[all …]
/drivers/firmware/scmi/
A Dmailbox.h19 #define _SCMI_MBOX_SHMEM_BY_IDX(node_id, idx) \ argument
20 COND_CODE_1(DT_PROP_HAS_IDX(node_id, shmem, idx), \
29 #define _SCMI_MBOX_CHAN_DBELL(node_id, name) \ argument
30 COND_CODE_1(DT_PROP_HAS_NAME(node_id, mboxes, name), \
31 (MBOX_DT_SPEC_GET(node_id, name)), \
38 .shmem = _SCMI_MBOX_SHMEM_BY_IDX(node_id, 0), \
39 .tx = _SCMI_MBOX_CHAN_DBELL(node_id, tx), \
50 _SCMI_MBOX_CHAN_DEFINE_PRIV_TX(node_id, proto); \
59 COND_CODE_1(DT_PROP_HAS_IDX(node_id, shmem, idx), \
68 #define SCMI_MBOX_PROTO_CHAN_DEFINE(node_id)\ argument
[all …]
/drivers/display/
A Ddisplay_ssd1363.c464 DIV_ROUND_UP(DT_PROP(node_id, width) * CONFIG_SSD1363_CONV_BUFFER_LINES, 1)
468 (ssd1363_grayscale_table_##node_id), (NULL))
471 static uint8_t conversion_buf##node_id[SSD1363_CONV_BUFFER_SIZE(node_id)]; \
476 .i2c = I2C_DT_SPEC_GET(node_id), \
477 .height = DT_PROP(node_id, height), \
500 DEVICE_DT_DEFINE(node_id, ssd1363_init_i2c, NULL, NULL, &config##node_id, \
504 static uint8_t conversion_buf##node_id[SSD1363_CONV_BUFFER_SIZE(node_id)]; \
511 node_id, SSD1363_WORD_SIZE(node_id) | SPI_OP_MODE_MASTER, 0), \
535 DEVICE_DT_DEFINE(node_id, ssd1363_init, NULL, NULL, &config##node_id, \
539 COND_CODE_1(DT_ON_BUS(node_id, i2c), \
[all …]
A Dssd1327.c461 DIV_ROUND_UP(DT_PROP(node_id, width) * CONFIG_SSD1327_CONV_BUFFER_LINES, 2)
465 (ssd1327_grayscale_table_##node_id), (NULL))
468 static uint8_t conversion_buf##node_id[SSD1327_CONV_BUFFER_SIZE(node_id)]; \
474 .i2c = I2C_DT_SPEC_GET(node_id), \
475 .height = DT_PROP(node_id, height), \
495 DEVICE_DT_DEFINE(node_id, ssd1327_init_i2c, NULL, &data##node_id, &config##node_id, \
499 static uint8_t conversion_buf##node_id[SSD1327_CONV_BUFFER_SIZE(node_id)]; \
507 node_id, SSD1327_WORD_SIZE(node_id) | SPI_OP_MODE_MASTER, 0), \
528 DEVICE_DT_DEFINE(node_id, ssd1327_init, NULL, &data##node_id, &config##node_id, \
532 COND_CODE_1(DT_ON_BUS(node_id, i2c), \
[all …]
A Ddisplay_ssd1320.c488 DIV_ROUND_UP(DT_PROP(node_id, width) * CONFIG_SSD1320_CONV_BUFFER_LINES, 2)
491 static uint8_t conversion_buf##node_id[SSD1320_CONV_BUFFER_SIZE(node_id)]; \
494 .i2c = I2C_DT_SPEC_GET(node_id), \
495 .height = DT_PROP(node_id, height), \
496 .width = DT_PROP(node_id, width), \
516 DEVICE_DT_DEFINE(node_id, ssd1320_init_i2c, NULL, &data##node_id, &config##node_id, \
520 static uint8_t conversion_buf##node_id[SSD1320_CONV_BUFFER_SIZE(node_id)]; \
525 node_id, SSD1320_WORD_SIZE(node_id) | SPI_OP_MODE_MASTER, 0), \
547 DEVICE_DT_DEFINE(node_id, ssd1320_init, NULL, &data##node_id, &config##node_id, \
551 COND_CODE_1(DT_ON_BUS(node_id, i2c), \
[all …]
A Ddisplay_sh1122.c458 .i2c = I2C_DT_SPEC_GET(node_id), \
459 .height = DT_PROP(node_id, height), \
460 .width = DT_PROP(node_id, width), \
461 .oscillator_freq = DT_PROP(node_id, oscillator_freq), \
462 .display_offset = DT_PROP(node_id, display_offset), \
463 .start_line = DT_PROP(node_id, start_line), \
479 DEVICE_DT_DEFINE(node_id, sh1122_init_i2c, NULL, &data##node_id, &config##node_id, \
488 node_id, SH1122_WORD_SIZE(node_id) | SPI_OP_MODE_MASTER, 0), \
509 DEVICE_DT_DEFINE(node_id, sh1122_init, NULL, &data##node_id, &config##node_id, \
513 COND_CODE_1(DT_ON_BUS(node_id, i2c), \
[all …]
A Dssd1322.c490 DT_PROP(node_id, segments_per_pixel), \
494 static uint8_t conversion_buf##node_id[SSD1322_CONV_BUFFER_SIZE(node_id)]; \
499 .height = DT_PROP(node_id, height), \
500 .width = DT_PROP(node_id, width), \
501 .column_offset = DT_PROP(node_id, column_offset), \
502 .row_offset = DT_PROP(node_id, row_offset), \
503 .start_line = DT_PROP(node_id, start_line), \
504 .mux_ratio = DT_PROP(node_id, mux_ratio), \
505 .grayscale_enhancement = DT_PROP(node_id, grayscale_enhancement), \
521 node_id, SSD1322_WORD_SIZE(node_id) | SPI_OP_MODE_MASTER, 0), \
[all …]
A Ddisplay_ssd1331.c349 .mipi_dev = DEVICE_DT_GET(DT_PARENT(node_id)), \
351 node_id, SSD1331_WORD_SIZE(node_id) | SPI_OP_MODE_MASTER, 0), \
352 .height = DT_PROP(node_id, height), \
353 .width = DT_PROP(node_id, width), \
354 .display_offset = DT_PROP(node_id, display_offset), \
355 .start_line = DT_PROP(node_id, start_line), \
356 .multiplex_ratio = DT_PROP(node_id, multiplex_ratio), \
357 .phase_length = DT_PROP(node_id, phase_length), \
358 .oscillator_freq = DT_PROP(node_id, oscillator_freq), \
359 .power_save = DT_PROP(node_id, power_save), \
[all …]
A Dssd1306.c535 node_id, SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_WORD_SET(8), 0)}, \
539 .data_cmd = GPIO_DT_SPEC_GET(node_id, data_cmd_gpios),
551 .reset = GPIO_DT_SPEC_GET_OR(node_id, reset_gpios, {0}), \
552 .supply = GPIO_DT_SPEC_GET_OR(node_id, supply_gpios, {0}), \
553 .height = DT_PROP(node_id, height), \
554 .width = DT_PROP(node_id, width), \
555 .segment_offset = DT_PROP(node_id, segment_offset), \
556 .page_offset = DT_PROP(node_id, page_offset), \
568 COND_CODE_1(DT_ON_BUS(node_id, spi), (SSD1306_CONFIG_SPI(node_id)), \
569 (SSD1306_CONFIG_I2C(node_id))) \
[all …]
A Ddisplay_st75256.c565 DIV_ROUND_UP(DT_PROP(node_id, width) * CONFIG_ST75256_CONV_BUFFER_LINES, 4)
583 static uint8_t conversion_buf##node_id[ST75256_CONV_BUFFER_SIZE(node_id)]; \
585 .height = DT_PROP(node_id, height), \
586 .width = DT_PROP(node_id, width), \
587 .booster_frequency = DT_PROP(node_id, booster_frequency), \
588 .bias_ratio = DT_PROP(node_id, bias_ratio), \
589 .lsb_invdir = DT_PROP(node_id, lsb_invdir), \
590 .flip_configuration = DT_PROP(node_id, flip_configuration), \
591 .duty = DT_PROP(node_id, duty), \
600 node_id, ST75256_WORD_SIZE(node_id) | SPI_OP_MODE_MASTER, 0), \
[all …]
A Ddisplay_ssd1351.c330 .mipi_dev = DEVICE_DT_GET(DT_PARENT(node_id)), \
332 node_id, SSD1351_WORD_SIZE(node_id) | SPI_OP_MODE_MASTER, 0), \
333 .height = DT_PROP(node_id, height), \
334 .width = DT_PROP(node_id, width), \
335 .display_offset = DT_PROP(node_id, display_offset), \
336 .start_line = DT_PROP(node_id, start_line), \
337 .multiplex_ratio = DT_PROP(node_id, multiplex_ratio), \
338 .phase_length = DT_PROP(node_id, phase_length), \
339 .oscillator_freq = DT_PROP(node_id, oscillator_freq), \
340 .precharge_time = DT_PROP(node_id, precharge_time), \
[all …]
A Ddisplay_st7567.c465 node_id, SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_WORD_SET(8), 0)}, \
476 .reset = GPIO_DT_SPEC_GET_OR(node_id, reset_gpios, {0}), \
477 .height = DT_PROP(node_id, height), \
478 .width = DT_PROP(node_id, width), \
479 .column_offset = DT_PROP(node_id, column_offset), \
480 .line_offset = DT_PROP(node_id, line_offset), \
481 .segment_invdir = DT_PROP(node_id, segment_invdir), \
482 .com_invdir = DT_PROP(node_id, com_invdir), \
486 COND_CODE_1(DT_ON_BUS(node_id, spi), (ST7567_CONFIG_SPI(node_id)), \
487 (ST7567_CONFIG_I2C(node_id))) }; \
[all …]
/drivers/pwm/
A Dpwm_nxp_s32_emios.c740 DT_ENUM_HAS_VALUE(node_id, pwm_mode, opwfmb)
746 #define EMIOS_PWM_IS_MODE_OPWMB(node_id) \ argument
747 DT_ENUM_HAS_VALUE(node_id, pwm_mode, opwmb)
750 DT_ENUM_HAS_VALUE(node_id, pwm_mode, saic)
753 EMIOS_PWM_IS_MODE_SAIC(node_id)
755 #define EMIOS_PWM_LOG(node_id, msg) \ argument
756 DT_NODE_PATH(node_id) ": " DT_PROP(node_id, pwm_mode) ": " msg \
809 BIT(DT_PROP(node_id, channel)) & DT_PROP(DT_GPARENT(node_id), internal_cnt),\
830 (EMIOS_PWM_VERIFY_MODE_SAIC(node_id)))
918 .FreezeEn = DT_PROP(node_id, freeze), \
[all …]
/drivers/clock_control/
A Dclock_control_renesas_rx_pclk_cgc.c16 #define MSTP_REGS_ELEM(node_id, prop, idx) \ argument
17 [DT_STRING_TOKEN_BY_IDX(node_id, prop, idx)] = \
18 (volatile uint32_t *)DT_REG_ADDR_BY_IDX(node_id, idx),
85 #define RENESAS_RX_CLOCK_SOURCE(node_id) \ argument
86 COND_CODE_1(DT_NODE_HAS_PROP(node_id, clocks), (DEVICE_DT_GET(DT_CLOCKS_CTLR(node_id))), \
87 DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(node_id))))
89 #define INIT_PCLK(node_id) \ argument
90 static const struct clock_control_rx_pclk_cfg clock_control_cfg_##node_id = { \
91 .clock_src_dev = RENESAS_RX_CLOCK_SOURCE(node_id), \
92 .clk_div = DT_INST_PROP_OR(node_id, div, 1), \
[all …]
A Dclock_control_renesas_ra_cgc.c16 #define MSTP_REGS_ELEM(node_id, prop, idx) \ argument
17 [DT_STRING_TOKEN_BY_IDX(node_id, prop, idx)] = \
18 (volatile uint32_t *)DT_REG_ADDR_BY_IDX(node_id, idx),
115 IF_ENABLED(DT_NODE_HAS_COMPAT(node_id, renesas_ra_cgc_pclk), \
116 (static const struct clock_control_ra_pclk_cfg node_id##_cfg = \
118 DT_NODE_HAS_PROP(node_id, clocks), \
119 (RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(node_id))), \
120 (RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_PARENT(node_id))))), \
121 .clk_div = DT_PROP(node_id, div)}; \
122 DEVICE_DT_DEFINE(node_id, &clock_control_ra_init_pclk, NULL, NULL, \
[all …]
/drivers/psi5/
A Dpsi5_nxp_s32.c238 const struct device *dev = DEVICE_DT_GET(DT_PARENT(node_id)); \
352 node_id)[PSI5_CHANNEL_CH_SFCR_COUNT] = { \
354 _PSI5_NXP_S32_CHANNEL_RX_SLOT_CONFIG, (), node_id)};
362 LISTIFY(PSI5_CHANNEL_CH_SFCR_COUNT, PSI5_NXP_S32_SLOT_CNT, (+), node_id), \
379 node_id) = { \
396 (DT_REG_ADDR(PSI5_NXP_S32_CHANNEL_NODE(n, i)) < (DT_REG_ADDR(node_id))) \
457 IRQ_CONNECT(DT_IRQ_BY_IDX(node_id, 0, irq), DT_IRQ_BY_IDX(node_id, 0, priority), \
458 _CONCAT(psi5_nxp_s32_channel_isr, node_id), DEVICE_DT_INST_GET(n), \
459 DT_IRQ_BY_IDX(node_id, 0, flags)); \
470 #define PSI5_NXP_S32_CHANNEL_BIT_MASK(node_id) BIT(DT_REG_ADDR(node_id)) argument
[all …]
/drivers/regulator/
A Dregulator_fake.c93 #define FAKE_DATA_NAME(node_id) _CONCAT(data_, DT_DEP_ORD(node_id)) argument
94 #define FAKE_CONF_NAME(node_id) _CONCAT(config_, DT_DEP_ORD(node_id)) argument
96 #define REGULATOR_FAKE_DEFINE(node_id) \ argument
97 static struct regulator_fake_data FAKE_DATA_NAME(node_id); \
99 static const struct regulator_fake_config FAKE_CONF_NAME(node_id) = { \
100 .common = REGULATOR_DT_COMMON_CONFIG_INIT(node_id), \
101 .is_enabled = DT_PROP(node_id, fake_is_enabled_in_hardware), \
104 DEVICE_DT_DEFINE(node_id, regulator_fake_init, NULL, \
105 &FAKE_DATA_NAME(node_id), &FAKE_CONF_NAME(node_id), \
/drivers/misc/nxp_s32_emios/
A Dnxp_s32_emios.c62 #define NXP_S32_EMIOS_MASTER_BUS_CONFIG(node_id) \ argument
64 .hwChannel = DT_PROP(node_id, channel), \
66 .masterBusPrescaler = DT_PROP(node_id, prescaler) - 1, \
67 .allowDebugMode = DT_PROP(node_id, freeze), \
93 #define EMIOS_INTERRUPT_DEFINE(node_id, prop, idx) \ argument
99 #define EMIOS_INTERRUPT_CONFIG(node_id, prop, idx) \ argument
101 IRQ_CONNECT(DT_IRQ_BY_IDX(node_id, idx, irq), \
102 DT_IRQ_BY_IDX(node_id, idx, priority), \
103 EMIOS_INTERRUPT_NAME(DT_STRING_TOKEN_BY_IDX(node_id, prop, idx)),\
104 DEVICE_DT_GET(node_id), \
[all …]
/drivers/misc/nxp_flexram/
A Dnxp_flexram.c26 #define IS_CHILD_RAM_TYPE(node_id, compat) DT_NODE_HAS_COMPAT_STATUS(node_id, compat, okay) argument
31 #define FIND_OCRAM_NODE(node_id) \ argument
32 COND_CODE_1(DT_NODE_HAS_COMPAT(node_id, mmio_sram), (node_id), ())
38 #define FIND_DTCM_NODE(node_id) \ argument
39 COND_CODE_1(DT_NODE_HAS_COMPAT(node_id, nxp_imx_dtcm), (node_id), ())
45 #define FIND_ITCM_NODE(node_id) \ argument
46 COND_CODE_1(DT_NODE_HAS_COMPAT(node_id, nxp_imx_itcm), (node_id), ())
55 #define PLUS_ONE_BANK(node_id, prop, idx) 1 argument
61 #define ADD_BANK_IF_OCRAM(node_id, prop, idx) \ argument
70 #define ADD_BANK_IF_DTCM(node_id, prop, idx) \ argument
[all …]
/drivers/sent/
A Dsent_nxp_s32.c178 LISTIFY(SRX_CNL_COUNT, SENT_NXP_S32_CHANNEL_ID_CNT, (+), node_id, n)
201 .BusTimeout = COND_CODE_0(DT_PROP(node_id, bus_timeout_cycles), \
204 DT_PROP(node_id, bus_timeout_cycles)))), \
205 .FastCrcCheckOff = DT_PROP(node_id, fast_crc) == \
207 .FastCrcType = DT_PROP(node_id, fast_crc) & \
211 .SlowCrcType = DT_PROP(node_id, short_serial_crc) == \
216 DT_PROP(node_id, successive_calib_pulse_method) == 1 ? \
219 DT_PROP(node_id, calib_pulse_tolerance_percent) == 20 ? \
221 .CrcStatusNibbleIncluding = DT_PROP(node_id, fast_crc) & \
227 &_CONCAT(sent_nxp_s32_channel_config, node_id),
[all …]
/drivers/stepper/step_dir/
A Dstep_dir_stepper_common.h45 #define STEP_DIR_STEPPER_DT_COMMON_CONFIG_INIT(node_id) \ argument
47 .step_pin = GPIO_DT_SPEC_GET(node_id, step_gpios), \
48 .dir_pin = GPIO_DT_SPEC_GET(node_id, dir_gpios), \
49 .dual_edge = DT_PROP_OR(node_id, dual_edge_step, false), \
50 .counter = DEVICE_DT_GET_OR_NULL(DT_PHANDLE(node_id, counter)), \
51 .invert_direction = DT_PROP(node_id, invert_direction), \
52 .timing_source = COND_CODE_1(DT_NODE_HAS_PROP(node_id, counter), \
100 #define STEP_DIR_STEPPER_DT_COMMON_DATA_INIT(node_id) \ argument
102 .dev = DEVICE_DT_GET(node_id), \

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