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Searched refs:opcode (Results 1 – 25 of 47) sorted by relevance

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/drivers/bluetooth/hci/
A Dhci_stm32wb0.c105 if (IN_RANGE(opcode, BT_HCI_OP_LE_SET_ADV_PARAM, BT_HCI_OP_LE_CREATE_CONN)) { in check_legacy_extended_call()
113 } else if ((opcode >= BT_HCI_OP_LE_SET_EXT_ADV_PARAM) && in check_legacy_extended_call()
114 (opcode <= BT_HCI_OP_LE_READ_PER_ADV_LIST_SIZE)) { in check_legacy_extended_call()
128 if (opcode == BT_HCI_OP_LE_CREATE_CONN || opcode == BT_HCI_OP_LE_EXT_CREATE_CONN || in check_legacy_extended_call()
129 opcode == BT_HCI_OP_LE_PER_ADV_CREATE_SYNC) { in check_legacy_extended_call()
137 params->opcode = sys_cpu_to_le16(opcode); in check_legacy_extended_call()
145 params->opcode = sys_cpu_to_le16(opcode); in check_legacy_extended_call()
164 op_code = hdr->opcode; in process_command()
171 for (i = 0; hci_command_table[i].opcode != 0; i++) { in process_command()
172 if (op_code == hci_command_table[i].opcode) { in process_command()
[all …]
A Dhci_nxp.c107 return bt_hci_cmd_send_sync(opcode, buf, NULL); in nxp_bt_send_vs_command()
117 uint16_t opcode = BT_OP(BT_OGF_VS, HCI_CMD_SET_BT_SLEEP_MODE_OCF); in nxp_bt_enable_controller_autosleep() local
125 return nxp_bt_send_vs_command(opcode, params, HCI_CMD_SET_BT_SLEEP_MODE_PARAM_LENGTH); in nxp_bt_enable_controller_autosleep()
130 uint16_t opcode = BT_OP(BT_OGF_VS, HCI_CMD_BT_HOST_SLEEP_CONFIG_OCF); in nxp_bt_set_host_sleep_config() local
137 return nxp_bt_send_vs_command(opcode, params, HCI_CMD_BT_HOST_SLEEP_CONFIG_PARAM_LENGTH); in nxp_bt_set_host_sleep_config()
144 uint16_t opcode = BT_OP(BT_OGF_VS, HCI_CMD_STORE_BT_CAL_DATA_OCF); in bt_nxp_set_calibration_data() local
148 return nxp_bt_send_vs_command(opcode, hci_cal_data_params, in bt_nxp_set_calibration_data()
155 uint16_t opcode = BT_OP(BT_OGF_VS, HCI_CMD_STORE_BT_CAL_DATA_ANNEX100_OCF); in bt_nxp_set_calibration_data_annex100() local
161 return nxp_bt_send_vs_command(opcode, hci_cal_data_annex100_params, in bt_nxp_set_calibration_data_annex100()
177 uint16_t opcode = BT_OP(BT_OGF_VS, HCI_SET_MAC_ADDR_CMD); in bt_nxp_set_mac_address() local
[all …]
/drivers/flash/
A Dflash_npcx_fiu_nor.c100 static int flash_npcx_uma_cmd_only(const struct device *dev, uint8_t opcode) in flash_npcx_uma_cmd_only() argument
102 struct npcx_uma_cfg cfg = { .opcode = opcode}; in flash_npcx_uma_cmd_only()
107 static int flash_npcx_uma_cmd_by_addr(const struct device *dev, uint8_t opcode, in flash_npcx_uma_cmd_by_addr() argument
110 struct npcx_uma_cfg cfg = { .opcode = opcode}; in flash_npcx_uma_cmd_by_addr()
116 static int flash_npcx_uma_read(const struct device *dev, uint8_t opcode, in flash_npcx_uma_read() argument
119 struct npcx_uma_cfg cfg = { .opcode = opcode, in flash_npcx_uma_read()
126 static int flash_npcx_uma_write(const struct device *dev, uint8_t opcode, in flash_npcx_uma_write() argument
129 struct npcx_uma_cfg cfg = { .opcode = opcode, in flash_npcx_uma_write()
139 struct npcx_uma_cfg cfg = { .opcode = opcode, in flash_npcx_uma_write_by_addr()
228 struct npcx_uma_cfg cfg = { .opcode = JESD216_CMD_READ_SFDP, in flash_npcx_nor_read_sfdp()
[all …]
A Dflash_andes_qspi_xip.c111 #define flash_andes_qspi_xip_cmd_read(dev, opcode, dest, length) \ argument
112 flash_andes_qspi_xip_access(dev, opcode, 0, 0, dest, length)
113 #define flash_andes_qspi_xip_cmd_write_data(dev, opcode, src, length) \ argument
114 flash_andes_qspi_xip_access(dev, opcode, ANDES_ACCESS_WRITE, 0, src, length)
115 #define flash_andes_qspi_xip_cmd_write(dev, opcode) \ argument
116 flash_andes_qspi_xip_access(dev, opcode, ANDES_ACCESS_WRITE, 0, NULL, 0)
118 flash_andes_qspi_xip_access(dev, opcode, ANDES_ACCESS_ADDRESSED, addr, dest, length)
120 flash_andes_qspi_xip_access(dev, opcode, ANDES_ACCESS_WRITE | ANDES_ACCESS_ADDRESSED, \
161 static __ramfunc int flash_andes_qspi_xip_access(const struct device *const dev, uint8_t opcode, in flash_andes_qspi_xip_access() argument
206 if (opcode == SPI_NOR_CMD_PP_1_1_4) { in flash_andes_qspi_xip_access()
[all …]
A Dspi_flash_at45.c113 const uint8_t opcode = CMD_READ_ID; in check_jedec_id() local
116 .buf = (void *)&opcode, in check_jedec_id()
117 .len = sizeof(opcode), in check_jedec_id()
122 .len = sizeof(opcode), in check_jedec_id()
160 const uint8_t opcode = CMD_READ_STATUS; in read_status_register() local
163 .buf = (void *)&opcode, in read_status_register()
164 .len = sizeof(opcode), in read_status_register()
169 .len = sizeof(opcode), in read_status_register()
412 opcode, in perform_erase_op()
537 .buf = (void *)&opcode, in power_down_op()
[all …]
A Dspi_nor.c386 uint8_t opcode, unsigned int access, in spi_nor_access() argument
394 uint8_t buf[6] = {opcode}; in spi_nor_access()
461 #define spi_nor_cmd_read(dev, opcode, dest, length) \ argument
462 spi_nor_access(dev, opcode, 0, 0, dest, length)
463 #define spi_nor_cmd_addr_read(dev, opcode, addr, dest, length) \ argument
464 spi_nor_access(dev, opcode, NOR_ACCESS_ADDRESSED, addr, dest, length)
466 spi_nor_access(dev, opcode, NOR_ACCESS_24BIT_ADDR | NOR_ACCESS_ADDRESSED, addr, dest, \
482 #define spi_nor_cmd_write(dev, opcode) \ argument
483 spi_nor_access(dev, opcode, NOR_ACCESS_WRITE, 0, NULL, 0)
484 #define spi_nor_cmd_addr_write(dev, opcode, addr, src, length) \ argument
[all …]
A Dflash_cadence_qspi_nor_ll.c59 int cad_qspi_set_read_config(struct cad_qspi_params *cad_params, uint32_t opcode, in cad_qspi_set_read_config() argument
68 sys_write32(CAD_QSPI_DEV_OPCODE(opcode) | CAD_QSPI_DEV_INST_TYPE(instr_type) | in cad_qspi_set_read_config()
77 int cad_qspi_set_write_config(struct cad_qspi_params *cad_params, uint32_t opcode, in cad_qspi_set_write_config() argument
85 sys_write32(CAD_QSPI_DEV_OPCODE(opcode) | CAD_QSPI_DEV_ADDR_TYPE(addr_type) | in cad_qspi_set_write_config()
150 int cad_qspi_stig_cmd(struct cad_qspi_params *cad_params, uint32_t opcode, uint32_t dummy) in cad_qspi_stig_cmd() argument
164 CAD_QSPI_FLASHCMD_OPCODE(opcode) | in cad_qspi_stig_cmd()
168 int cad_qspi_stig_read_cmd(struct cad_qspi_params *cad_params, uint32_t opcode, uint32_t dummy, in cad_qspi_stig_read_cmd() argument
185 uint32_t cmd = CAD_QSPI_FLASHCMD_OPCODE(opcode) | CAD_QSPI_FLASHCMD_ENRDDATA(1) | in cad_qspi_stig_read_cmd()
205 int cad_qspi_stig_wr_cmd(struct cad_qspi_params *cad_params, uint32_t opcode, uint32_t dummy, in cad_qspi_stig_wr_cmd() argument
222 uint32_t cmd = CAD_QSPI_FLASHCMD_OPCODE(opcode) | CAD_QSPI_FLASHCMD_ENRDDATA(0) | in cad_qspi_stig_wr_cmd()
[all …]
A Dflash_andes_qspi.c37 #define flash_andes_qspi_cmd_read(dev, opcode, dest, length) \ argument
38 flash_andes_qspi_access(dev, opcode, 0, 0, dest, length)
39 #define flash_andes_qspi_cmd_addr_read(dev, opcode, addr, dest, length) \ argument
40 flash_andes_qspi_access(dev, opcode, ANDES_ACCESS_ADDRESSED, addr, \
43 flash_andes_qspi_access(dev, opcode, ANDES_ACCESS_WRITE, 0, NULL, 0)
45 flash_andes_qspi_access(dev, opcode, \
135 uint8_t opcode, uint8_t access, off_t addr, in flash_andes_qspi_access() argument
160 if ((opcode == FLASH_ANDES_CMD_4PP) || in flash_andes_qspi_access()
161 (opcode == FLASH_ANDES_CMD_4READ)) { in flash_andes_qspi_access()
183 switch (opcode) { in flash_andes_qspi_access()
[all …]
A DKconfig.at4529 Use the Read-Modify-Write command (opcode 0x58) instead of the default
30 Main Memory Program without Built-In Erase (opcode 0x02). This allows
A Dflash_npcx_fiu_qspi.h44 uint8_t opcode; member
A Dnrf_qspi_nor.c445 .opcode = cmd->op_code, in qspi_send_cmd()
462 uint8_t opcode = SPI_NOR_CMD_RDSR; in qspi_rdsr() local
468 opcode = SPI_NOR_CMD_RDSR2; in qspi_rdsr()
476 .op_code = opcode, in qspi_rdsr()
505 uint8_t opcode = SPI_NOR_CMD_WRSR; in qspi_wrsr() local
542 opcode = SPI_NOR_CMD_WRSR2; in qspi_wrsr()
554 .op_code = opcode, in qspi_wrsr()
752 .opcode = JESD216_CMD_READ_SFDP, in qspi_sfdp_read()
/drivers/sdhc/
A Dsdhc_renesas_ra.c171 .opcode = cmd->opcode, in sdhc_ra_request()
201 switch (cmd->opcode) { in sdhc_ra_request()
283 ra_cmd.opcode |= SDHI_PRV_CMD_C_ACMD; in sdhc_ra_request()
303 if (priv->app_cmd && cmd->opcode == SD_APP_SET_BUS_WIDTH) { in sdhc_ra_request()
305 ra_cmd.opcode |= SDHI_PRV_CMD_C_ACMD; in sdhc_ra_request()
326 ra_cmd.opcode = cmd->opcode | SDHI_PRV_CMD_C_ACMD; in sdhc_ra_request()
348 ra_cmd.opcode, ra_cmd.arg); in sdhc_ra_request()
376 ra_cmd.opcode, ra_cmd.arg); in sdhc_ra_request()
394 LOG_INF("SDHC driver: command %u not supported", cmd->opcode); in sdhc_ra_request()
398 if (ra_cmd.opcode == SD_ALL_SEND_CID || ra_cmd.opcode == SD_SEND_CSD) { in sdhc_ra_request()
[all …]
A Dsdhc_max32.c20 static int cmd_opcode_converter(int opcode, unsigned int *cmd);
199 switch (cmd->opcode) { in sdhc_max32_request()
217 ret = cmd_opcode_converter(cmd->opcode, &mxc_cmd); in sdhc_max32_request()
232 LOG_ERR("MXC_SDHC_SendCommand error:%d, SD opcode: %d", ret, cmd->opcode); in sdhc_max32_request()
301 static int cmd_opcode_converter(int opcode, unsigned int *cmd) in cmd_opcode_converter() argument
303 switch (opcode) { in cmd_opcode_converter()
379 LOG_ERR("Opcode convert error %d", opcode); in cmd_opcode_converter()
A Dsdhc_cdns.c68 cdns_sdmmc_cmd.cmd_idx = cmd->opcode; in sdhc_cdns_request()
85 if (cmd->opcode == SD_READ_SINGLE_BLOCK || cmd->opcode == SD_APP_SEND_SCR || in sdhc_cdns_request()
86 cmd->opcode == SD_READ_MULTIPLE_BLOCK) { in sdhc_cdns_request()
A Dsdhc_renesas_ra.h21 uint32_t opcode; member
A Dsdhc_esp32.c575 (cmd->opcode == SD_WRITE_MULTIPLE_BLOCK || cmd->opcode == SD_READ_MULTIPLE_BLOCK); in cmd_needs_auto_stop()
582 res.cmd_index = cmd->opcode; in make_hw_cmd()
583 if (cmd->opcode == SD_STOP_TRANSMISSION) { in make_hw_cmd()
585 } else if (cmd->opcode == SD_GO_IDLE_STATE) { in make_hw_cmd()
590 if (cmd->opcode == SD_GO_IDLE_STATE) { in make_hw_cmd()
700 data->s_is_app_cmd = (ret == ESP_OK && cmdinfo->opcode == SD_APP_CMD); in sdmmc_host_do_transaction()
1091 .opcode = cmd->opcode, in sdhc_esp32_request()
1115 switch (cmd->opcode) { in sdhc_esp32_request()
1175 LOG_INF("SDHC driver: command %u not supported", cmd->opcode); in sdhc_esp32_request()
1192 cmd->opcode, cmd->arg, ret_esp, esp_cmd.error); in sdhc_esp32_request()
[all …]
A Dsdhc_spi.c413 cmd_buf[0] = (cmd->opcode & SD_SPI_CMD); in sdhc_spi_send_cmd()
419 LOG_DBG("cmd%d arg 0x%x", cmd->opcode, cmd->arg); in sdhc_spi_send_cmd()
640 .opcode = SD_STOP_TRANSMISSION, in sdhc_spi_request()
663 if ((cmd->opcode == SD_WRITE_SINGLE_BLOCK) || in sdhc_spi_request()
664 (cmd->opcode == SD_WRITE_MULTIPLE_BLOCK)) { in sdhc_spi_request()
669 if (ret || (cmd->opcode == SD_READ_MULTIPLE_BLOCK)) { in sdhc_spi_request()
A Dxlnx_sdhc.c228 uint16_t command = (cmd->opcode << XLNX_SDHC_OPCODE_SHIFT); in xlnx_sdhc_cmd_frame()
269 if ((cmd->opcode == SD_APP_CMD) && (slottype == XLNX_SDHC_EMMC_SLOT)) { in xlnx_sdhc_cmd_frame()
296 if ((cmd->opcode == SD_SEND_TUNING_BLOCK) || (cmd->opcode == MMC_SEND_TUNING_BLOCK)) { in xlnx_sdhc_cmd_response()
384 if ((cmd->opcode != SD_SEND_TUNING_BLOCK) && (cmd->opcode != MMC_SEND_TUNING_BLOCK)) { in xlnx_sdhc_cmd()
520 switch (cmd->opcode) { in xlnx_sdhc_request()
1233 cmd.opcode = MMC_SEND_TUNING_BLOCK; in xlnx_sdhc_card_tuning()
1235 cmd.opcode = SD_SEND_TUNING_BLOCK; in xlnx_sdhc_card_tuning()
A Dsam_hsmci.c273 cmdr |= HSMCI_CMDR_CMDNB(cmd->opcode) | HSMCI_CMDR_MAXLAT_64; in sam_hsmci_send_cmd()
492 LOG_DBG("%s(opcode=%d, arg=%08x, data=%08x, rsptype=%d)", __func__, cmd->opcode, cmd->arg, in sam_hsmci_request_inner()
495 if (cmd->opcode == SD_GO_IDLE_STATE) { in sam_hsmci_request_inner()
508 switch (cmd->opcode) { in sam_hsmci_request_inner()
612 .opcode = SD_STOP_TRANSMISSION, .arg = 0, .response_type = SD_RSP_TYPE_NONE}; in sam_hsmci_abort()
A Dsdhc_esp32.h89 uint32_t opcode; /*!< SD or MMC command index */ member
/drivers/sensor/s11059/
A Ds11059.c126 const uint8_t opcode[] = {S11059_REG_ADDR_CONTROL, control}; in s11059_control_write() local
128 return i2c_write_dt(&cfg->bus, opcode, sizeof(opcode)); in s11059_control_write()
134 const uint8_t opcode[] = {S11059_REG_ADDR_MANUAL_TIMING, manual_time >> 8, in s11059_manual_timing_write() local
137 return i2c_write_dt(&cfg->bus, opcode, sizeof(opcode)); in s11059_manual_timing_write()
/drivers/sensor/rohm/bh1750/
A Dbh1750.c50 static int bh1750_opcode_read(const struct device *dev, uint8_t opcode, in bh1750_opcode_read() argument
56 rc = i2c_burst_read_dt(&cfg->bus, opcode, (uint8_t *)val, 2); in bh1750_opcode_read()
65 static int bh1750_opcode_write(const struct device *dev, uint8_t opcode) in bh1750_opcode_write() argument
69 return i2c_write_dt(&cfg->bus, &opcode, 1); in bh1750_opcode_write()
/drivers/lora/
A Dsx126x.c182 uint8_t SX126xReadCommand(RadioCommands_t opcode, in SX126xReadCommand() argument
186 opcode, in SX126xReadCommand()
193 opcode, size); in SX126xReadCommand()
200 void SX126xWriteCommand(RadioCommands_t opcode, uint8_t *buffer, uint16_t size) in SX126xWriteCommand() argument
203 opcode, in SX126xWriteCommand()
207 opcode, size); in SX126xWriteCommand()
/drivers/ethernet/
A Deth_enc424j600.c98 static void enc424j600_modify_sfru(const struct device *dev, uint8_t opcode, in enc424j600_modify_sfru() argument
112 buf[0] = opcode; in enc424j600_modify_sfru()
159 static void enc424j600_write_mem(const struct device *dev, uint8_t opcode, in enc424j600_write_mem() argument
163 uint8_t buf[1] = { opcode }; in enc424j600_write_mem()
185 static void enc424j600_read_mem(const struct device *dev, uint8_t opcode, in enc424j600_read_mem() argument
189 uint8_t buf[1] = { opcode }; in enc424j600_read_mem()
/drivers/dma/
A Ddma_iproc_pax_v1.h79 uint64_t opcode : 4; /*opcode 59:56*/ member

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