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Searched refs:phy_addr (Results 1 – 17 of 17) sorted by relevance

/drivers/ethernet/
A Dphy_xlnx_gem.c37 uint32_t base_addr, uint8_t phy_addr, in phy_xlnx_gem_mdio_read() argument
61 base_addr, phy_addr, reg_addr); in phy_xlnx_gem_mdio_read()
94 base_addr, phy_addr, reg_addr); in phy_xlnx_gem_mdio_read()
116 uint32_t base_addr, uint8_t phy_addr, in phy_xlnx_gem_mdio_write() argument
140 base_addr, phy_addr, reg_addr); in phy_xlnx_gem_mdio_write()
175 base_addr, phy_addr, reg_addr); in phy_xlnx_gem_mdio_write()
222 dev->name, dev_data->phy_addr); in phy_xlnx_gem_marvell_alaska_reset()
291 dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_cfg()
296 dev->name, dev_data->phy_addr); in phy_xlnx_gem_marvell_alaska_cfg()
634 dev->name, dev_data->phy_addr); in phy_xlnx_gem_ti_dp83822_reset()
[all …]
A Dphy_gecko.c54 static int mdio_bus_send(ETH_TypeDef *eth, uint8_t phy_addr, uint8_t reg_addr, in mdio_bus_send() argument
63 | ((phy_addr << _ETH_PHYMNGMNT_PHYADDR_SHIFT) in mdio_bus_send()
84 uint8_t phy_addr = phy->address; in phy_read() local
87 retval = mdio_bus_send(eth, phy_addr, reg_addr, 1, 0); in phy_read()
103 uint8_t phy_addr = phy->address; in phy_write() local
105 return mdio_bus_send(eth, phy_addr, reg_addr, 0, value); in phy_write()
A Dphy_cyclonev.c100 uint16_t phy_addr; in alt_eth_phy_write_register() local
106 phy_addr = PHY_ADDR; in alt_eth_phy_write_register()
111 tmpreg |= EMAC_GMAC_GMII_ADDR_PA_SET(phy_addr); in alt_eth_phy_write_register()
147 uint16_t phy_addr; in alt_eth_phy_read_register() local
153 phy_addr = PHY_ADDR; in alt_eth_phy_read_register()
158 tmpreg |= EMAC_GMAC_GMII_ADDR_PA_SET(phy_addr); in alt_eth_phy_read_register()
A Deth_numaker.c56 uint32_t phy_addr; member
725 eth_phy_addr = cfg->phy_addr; in eth_numaker_init()
786 .phy_addr = DT_INST_PROP(0, phy_addr),
A Deth_adin2111_priv.h263 const uint16_t phy_addr; member
A Deth_xlnx_gem_priv.h482 .phy_addr = 0,\
749 uint8_t phy_addr; member
A Deth_adin2111.c1169 cfg->phy_addr, cfg->port_idx); in adin2111_port_iface_init()
1527 #define ADIN2111_MDIO_PHY_BY_ADDR(adin_n, phy_addr) \ argument
1528 DEVICE_DT_GET(DT_CHILD(DT_INST_CHILD(adin_n, mdio), ethernet_phy_##phy_addr))
1541 .phy_addr = phy_n, \
/drivers/ethernet/phy/
A Dphy_adin2111.c93 uint8_t phy_addr; member
114 return mdio_read(cfg->mdio, cfg->phy_addr, reg, val); in phy_adin2111_c22_read()
122 return mdio_write(cfg->mdio, cfg->phy_addr, reg, val); in phy_adin2111_c22_write()
159 return mdio_read_c45(cfg->mdio, cfg->phy_addr, devad, reg, val); in phy_adin2111_c45_read()
456 cfg->phy_addr, ret); in phy_adin2111_init()
463 cfg->phy_addr, ret); in phy_adin2111_init()
472 LOG_INF("PHY %u ID %X", cfg->phy_addr, phy_id); in phy_adin2111_init()
540 LOG_INF("PHY %u 2.4V mode %s", cfg->phy_addr, in phy_adin2111_init()
545 cfg->phy_addr); in phy_adin2111_init()
563 cfg->phy_addr); in phy_adin2111_init()
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A Dphy_mii.c27 uint8_t phy_addr; member
74 return mdio_read(cfg->mdio, cfg->phy_addr, reg_addr, value); in phy_mii_reg_read()
91 return mdio_write(cfg->mdio, cfg->phy_addr, reg_addr, value); in phy_mii_reg_write()
186 LOG_INF("PHY (%d) is down", cfg->phy_addr); in update_link_state()
205 cfg->phy_addr, in update_link_state()
263 cfg->phy_addr); in check_autonegotiation_completion()
304 cfg->phy_addr, in check_autonegotiation_completion()
379 cfg->phy_addr); in phy_mii_cfg_link()
514 LOG_ERR("No PHY found at address %d", cfg->phy_addr); in phy_mii_initialize_dynamic_link()
519 LOG_INF("PHY (%d) ID %X", cfg->phy_addr, phy_id); in phy_mii_initialize_dynamic_link()
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A Dphy_microchip_t1s.c93 uint8_t phy_addr; member
117 ret = mdio_read(cfg->mdio, cfg->phy_addr, reg, (uint16_t *)data); in phy_mc_t1s_read()
131 ret = mdio_write(cfg->mdio, cfg->phy_addr, reg, (uint16_t)data); in phy_mc_t1s_write()
143 ret = mdio_write(cfg->mdio, cfg->phy_addr, MII_MMD_ACR, devad); in mdio_setup_c45_indirect_access()
148 ret = mdio_write(cfg->mdio, cfg->phy_addr, MII_MMD_AADR, reg); in mdio_setup_c45_indirect_access()
153 return mdio_write(cfg->mdio, cfg->phy_addr, MII_MMD_ACR, devad | BIT(14)); in mdio_setup_c45_indirect_access()
164 return mdio_read_c45(cfg->mdio, cfg->phy_addr, devad, reg, val); in phy_mc_t1s_c45_read()
176 ret = mdio_read(cfg->mdio, cfg->phy_addr, MII_MMD_AADR, val); in phy_mc_t1s_c45_read()
191 return mdio_write_c45(cfg->mdio, cfg->phy_addr, devad, reg, val); in phy_mc_t1s_c45_write()
203 ret = mdio_write(cfg->mdio, cfg->phy_addr, MII_MMD_AADR, val); in phy_mc_t1s_c45_write()
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A Dphy_dm8806.c25 uint8_t phy_addr; member
554 LOG_ERR("Invalid speed %d for PHY (%d)", adv_speeds, cfg->phy_addr); in phy_dm8806_cfg_link()
559 ret = phy_dm8806_read_reg(dev, cfg->phy_addr, DM8806_PORTX_PHY_CONTROL_REGISTER, &data); in phy_dm8806_cfg_link()
566 ret = phy_dm8806_write_reg(dev, cfg->phy_addr, DM8806_PORTX_PHY_CONTROL_REGISTER, data); in phy_dm8806_cfg_link()
574 ret = phy_dm8806_read_reg(dev, cfg->phy_addr, DM8806_PORTX_PHY_CONTROL_REGISTER, &data); in phy_dm8806_cfg_link()
581 ret = phy_dm8806_write_reg(dev, cfg->phy_addr, DM8806_PORTX_PHY_CONTROL_REGISTER, data); in phy_dm8806_cfg_link()
589 ret = phy_dm8806_read_reg(dev, cfg->phy_addr, DM8806_PORTX_PHY_CONTROL_REGISTER, &data); in phy_dm8806_cfg_link()
597 ret = phy_dm8806_write_reg(dev, cfg->phy_addr, DM8806_PORTX_PHY_CONTROL_REGISTER, data); in phy_dm8806_cfg_link()
605 ret = phy_dm8806_read_reg(dev, cfg->phy_addr, DM8806_PORTX_PHY_CONTROL_REGISTER, &data); in phy_dm8806_cfg_link()
612 ret = phy_dm8806_write_reg(dev, cfg->phy_addr, DM8806_PORTX_PHY_CONTROL_REGISTER, data); in phy_dm8806_cfg_link()
[all …]
A Dphy_tja11xx.c32 uint8_t phy_addr; member
49 return mdio_read(cfg->mdio, cfg->phy_addr, reg, val); in phy_tja11xx_c22_read()
56 return mdio_write(cfg->mdio, cfg->phy_addr, reg, val); in phy_tja11xx_c22_write()
232 .phy_addr = DT_INST_REG_ADDR(n), \
A Dphy_tja1103.c68 uint8_t phy_addr; member
87 return mdio_read(cfg->mdio, cfg->phy_addr, reg, val); in phy_tja1103_c22_read()
94 return mdio_write(cfg->mdio, cfg->phy_addr, reg, val); in phy_tja1103_c22_write()
102 return mdio_write_c45(cfg->mdio, cfg->phy_addr, devad, reg, val); in phy_tja1103_c45_write()
110 return mdio_read_c45(cfg->mdio, cfg->phy_addr, devad, reg, val); in phy_tja1103_c45_read()
343 LOG_ERR("Unable to obtain PHY ID for device 0x%x", cfg->phy_addr); in phy_tja1103_init()
419 .phy_addr = DT_INST_REG_ADDR(n), \
/drivers/mdio/
A Dmdio_xmc4xxx.c51 static int mdio_xmc4xxx_transfer(const struct device *dev, uint8_t phy_addr, uint8_t reg_addr, in mdio_xmc4xxx_transfer() argument
74 FIELD_PREP(ETH_GMII_ADDRESS_PA_Msk, phy_addr) | in mdio_xmc4xxx_transfer()
94 static int mdio_xmc4xxx_read(const struct device *dev, uint8_t phy_addr, uint8_t reg_addr, in mdio_xmc4xxx_read() argument
97 return mdio_xmc4xxx_transfer(dev, phy_addr, reg_addr, 0, 0, data); in mdio_xmc4xxx_read()
100 static int mdio_xmc4xxx_write(const struct device *dev, uint8_t phy_addr, in mdio_xmc4xxx_write() argument
103 return mdio_xmc4xxx_transfer(dev, phy_addr, reg_addr, 1, data, NULL); in mdio_xmc4xxx_write()
/drivers/crypto/
A Dcrypto_smartbond.c403 uint32_t phy_addr = black_orca_phy_addr((uint32_t)in_buf); in crypto_smartbond_set_in_out_buf() local
405 if (IS_QSPIF_CACHED_ADDRESS(phy_addr)) { in crypto_smartbond_set_in_out_buf()
410 phy_addr += (MCU_QSPIF_M_BASE - MCU_QSPIF_M_CACHED_BASE); in crypto_smartbond_set_in_out_buf()
411 } else if (IS_OTP_ADDRESS(phy_addr)) { in crypto_smartbond_set_in_out_buf()
413 phy_addr += (MCU_OTP_M_P_BASE - MCU_OTP_M_BASE); in crypto_smartbond_set_in_out_buf()
416 AES_HASH->CRYPTO_FETCH_ADDR_REG = phy_addr; in crypto_smartbond_set_in_out_buf()
/drivers/i2c/
A Di2c_dw.h144 uintptr_t phy_addr; member
A Di2c_dw.c202 return (void *)(dw->phy_addr + DW_IC_REG_DATA_CMD); in i2c_dw_dr_phy_addr()
1271 dw->phy_addr = mbar.phys_addr; in i2c_dw_initialize()
1273 sys_write32((uint32_t)dw->phy_addr, in i2c_dw_initialize()
1275 sys_write32((uint32_t)(dw->phy_addr >> DMA_INTEL_LPSS_ADDR_RIGHT_SHIFT), in i2c_dw_initialize()
1277 LOG_DBG("i2c instance physical addr: [0x%lx], virtual addr: [0x%lx]", dw->phy_addr, in i2c_dw_initialize()

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