Searched refs:platform (Results 1 – 25 of 25) sorted by relevance
42 struct afbr_s50_platform_data platform; member146 struct afbr_s50_platform_data *platform; in data_ready_callback() local160 struct afbr_s50_data *data = CONTAINER_OF(platform, struct afbr_s50_data, platform); in data_ready_callback()299 err = afbr_s50_platform_init(&data->platform); in afbr_s50_init()306 if (data->platform.argus.handle == NULL) { in afbr_s50_init()313 data->platform.argus.id, in afbr_s50_init()354 if (drv_data->platform.argus.id == slave) { in afbr_s50_platform_get_by_id()355 *data = &drv_data->platform; in afbr_s50_platform_get_by_id()369 if (drv_data->platform.argus.handle == hnd) { in afbr_s50_platform_get_by_hnd()370 *data = &drv_data->platform; in afbr_s50_platform_get_by_hnd()[all …]
30 const struct device *const platform; member44 mdic = DEVICE_MMIO_GET(cfg->platform) + INTEL_IGC_MDIC_OFFSET; in intel_igc_mdio()172 .platform = DEVICE_DT_GET(DT_INST_PARENT(n)), \
9 and PIC64GX platform.
12 Enable the PWM driver for the SiFive Freedom platform
14 platform provides the standard "system clock driver" interfaces.
13 platform provides the standard "system clock driver" interfaces.
12 platform provides the standard "system clock driver" interfaces.
109 under reset. Note that this requires that the platform provides a timer
11 The timers (TMR) present in the platform are used as timers.
11 The dualtimer (DTMR) present in the platform is used as a timer.
17 Size of response buffer used for ASYNC transactions.For Intel Agilex platform
81 GIC redistributor on Some platform are connected to a non-coherent90 GIC ITS on Some platform are connected to a non-coherent downstream
16 platform-specific code, to acquire a reference to the syscon node and
20 and MMU based platform is also provided.
81 However, this is a number by experience and could be platform specific.
36 Set from SOC level configuration if the platform is meant to use the
71 int "Sync period per platform"
457 const struct device *const platform; member
312 bdf = eth_intel_get_pcie_bdf(cfg->platform); in eth_intel_igc_pcie_msix_setup()1172 data->base = DEVICE_MMIO_GET(cfg->platform); in eth_intel_igc_init()1312 .platform = DEVICE_DT_GET(DT_INST_PARENT(n)), \
17 any serial capable platform and communicates with Espressif chips
163 Don't enable this config if the platform implements the Deep-Sx
76 additional platform specific knowledge may need to be added as
295 platform layer. The memory should be pointed to by the
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