1/*
2 * Copyright (c) 2022 Benjamin Björnsson <benjamin.bjornsson@gmail.com>.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8
9/ {
10	leds {
11		compatible = "gpio-leds";
12		red_led: led_0 {
13			gpios = <&gpiok 5 GPIO_ACTIVE_LOW>;
14		};
15		green_led: led_1 {
16			gpios = <&gpiok 6 GPIO_ACTIVE_LOW>;
17		};
18		blue_led: led_2 {
19			gpios = <&gpiok 7 GPIO_ACTIVE_LOW>;
20		};
21	};
22
23	otghs_ulpi_phy: otghs_ulpis_phy {
24		compatible = "usb-ulpi-phy";
25		reset-gpios = < &gpioj 4 GPIO_ACTIVE_LOW >;
26		#phy-cells = <0>;
27	};
28
29	aliases {
30		led0 = &red_led;
31		led1 = &green_led;
32		led2 = &blue_led;
33		sdhc0 = &sdhc;
34	};
35};
36
37&clk_hsi48 {
38	/* HSI48 required for USB */
39	status = "okay";
40};
41
42&rcc {
43	d1cpre = < 1 >;
44	hpre = < 2 >;
45	d1ppre = < 2 >;
46	d2ppre1 = < 2 >;
47	d2ppre2 = < 2 >;
48	d3ppre = < 2 >;
49};
50
51/* UART0 in datasheet */
52&uart4 {
53	pinctrl-0 = <&uart4_tx_pa0 &uart4_rx_pi9>;
54	pinctrl-names = "default";
55	current-speed = <115200>;
56};
57
58/* UART1 in datasheet */
59&usart1 {
60	pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
61	pinctrl-names = "default";
62	current-speed = <115200>;
63};
64
65/* UART2 in datasheet */
66&usart6 {
67	pinctrl-0 = <&usart6_tx_pg14 &usart6_rx_pg9>;
68	pinctrl-names = "default";
69	current-speed = <115200>;
70};
71
72/* UART3 in datasheet */
73&uart8 {
74	pinctrl-0 = <&uart8_tx_pj8 &uart8_rx_pj9>;
75	pinctrl-names = "default";
76	current-speed = <115200>;
77};
78
79/* I2C0 in datasheet */
80&i2c3 {
81	pinctrl-0 = <&i2c3_scl_ph7 &i2c3_sda_ph8>;
82	pinctrl-names = "default";
83	clock-frequency = <I2C_BITRATE_FAST>;
84};
85
86/* I2C1 in datasheet */
87zephyr_i2c: &i2c1 {
88	pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>;
89	pinctrl-names = "default";
90	clock-frequency = <I2C_BITRATE_FAST>;
91};
92
93/* I2C2 in datasheet */
94&i2c4 {
95	pinctrl-0 = <&i2c4_scl_ph11 &i2c4_sda_ph12>;
96	pinctrl-names = "default";
97	clock-frequency = <I2C_BITRATE_FAST>;
98};
99
100/* I2C3 in datasheet */
101&i2c3 {
102	pinctrl-0 = <&i2c3_scl_ph7 &i2c3_sda_ph8>;
103	pinctrl-names = "default";
104	clock-frequency = <I2C_BITRATE_FAST>;
105};
106
107/* SPI1 in datasheet */
108&spi2 {
109	pinctrl-0 = <&spi2_nss_pi0 &spi2_sck_pi1
110		     &spi2_miso_pc2 &spi2_mosi_pc3>;
111	pinctrl-names = "default";
112};
113
114&fdcan1 {
115	pinctrl-0 = <&fdcan1_rx_pb8 &fdcan1_tx_ph13>;
116	pinctrl-names = "default";
117	clocks = <&rcc STM32_CLOCK(APB1_2, 8)>,
118		 <&rcc STM32_SRC_PLL1_Q FDCAN_SEL(1)>;
119};
120
121&rtc {
122	status = "okay";
123};
124
125&mailbox {
126	status = "okay";
127};
128
129&fmc {
130	status = "okay";
131	pinctrl-0 = < &fmc_d2_pd0 &fmc_d3_pd1 &fmc_d13_pd8 &fmc_d14_pd9
132		      &fmc_d15_pd10 &fmc_d0_pd14 &fmc_d1_pd15 &fmc_nbl0_pe0
133		      &fmc_nbl1_pe1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9
134		      &fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13
135		      &fmc_d11_pe14 &fmc_d12_pe15 &fmc_a0_pf0 &fmc_a1_pf1
136		      &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4 &fmc_a5_pf5
137		      &fmc_sdnras_pf11 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14
138		      &fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1 &fmc_a12_pg2
139		      &fmc_a14_pg4 /* FMC_BA0 */ &fmc_a15_pg5 /* FMC_BA1 */
140		      &fmc_sdclk_pg8 &fmc_sdncas_pg15 &fmc_sdcke0_ph2 &fmc_sdne0_ph3
141		      &fmc_sdnwe_ph5 >;
142	pinctrl-names = "default";
143	st,mem-swap = "disable";
144	sdram {
145		status = "okay";
146		mode-register = < 0x220 >;
147
148		/** From Arduino github repository:
149		 *  RefreshRate = 64 ms / 8192 cyc = 7.8125 us/cyc
150		 *  RefreshCycles = 7.8125 us * 90 MHz = 703
151		 *  According to the formula on p.1665 of the reference manual,
152		 *  we also need to subtract 20 from the value, so the target
153		 *  refresh rate is 703 - 20 = 683.
154		 */
155		refresh-rate = < 683 >;
156		num-auto-refresh = < 8 >;
157
158		bank@0 {
159			reg = < 0 >;
160			st,sdram-control = < STM32_FMC_SDRAM_NC_8
161					     STM32_FMC_SDRAM_NR_12
162					     STM32_FMC_SDRAM_MWID_16
163					     STM32_FMC_SDRAM_NB_4
164					     STM32_FMC_SDRAM_CAS_2
165					     STM32_FMC_SDRAM_SDCLK_PERIOD_2
166					     STM32_FMC_SDRAM_RBURST_ENABLE
167					     STM32_FMC_SDRAM_RPIPE_0 >;
168			st,sdram-timing = < 2 7 5 7 2 3 3 >;
169		};
170	};
171};
172
173&quadspi {
174	pinctrl-0 = < &quadspi_bk1_io0_pd11
175		      &quadspi_bk1_io1_pd12
176		      &quadspi_bk1_io2_pf7
177		      &quadspi_bk1_io3_pd13
178		      &quadspi_bk1_ncs_pg6
179		      &quadspi_clk_pf10 >;
180	pinctrl-names = "default";
181	status = "okay";
182
183	mx25l12833f: qspi-nor-flash@0 {
184		compatible = "st,stm32-qspi-nor";
185		reg = <0>;
186		size = <DT_SIZE_M(128)>; /* 128 Mbits */
187		qspi-max-frequency = < 40000000 >;
188		cs-high-time = <2>; /* >= 30 ns */
189		sfdp-bfp = [ e5 20 f1 ff  ff ff ff 07  44 eb 08 6b  08 3b 04 bb
190			     fe ff ff ff  ff ff 00 ff  ff ff 44 eb  0c 20 0f 52
191			     10 d8 00 ff  82 41 bd 00  81 e5 7b c6  44 03 67 38
192			     30 b0 30 b0  f7 bd d5 5c  4a be 29 ff  e1 d0 ff ff ];
193		jedec-id = [ 66 66 20 ];
194		spi-bus-width = <4>;
195		status = "okay";
196
197		partitions {
198			compatible = "fixed-partitions";
199			#address-cells = < 1 >;
200			#size-cells = < 1 >;
201
202			storage_partition: partition@0 {
203				label = "storage";
204				reg=< 0x0 DT_SIZE_K(15872) >;
205			};
206
207			wifi_firmware: partition@f80000 {
208				label = "wifi-firmware";
209				reg = < 0xf80000 DT_SIZE_K(512) >;
210			};
211		};
212	};
213};
214
215&rng {
216	status = "okay";
217};
218
219&mac {
220	pinctrl-0 = < &eth_ref_clk_pa1
221		      &eth_crs_dv_pa7
222		      &eth_rxd0_pc4
223		      &eth_rxd1_pc5
224		      &eth_tx_en_pg11
225		      &eth_txd1_pg12
226		      &eth_txd0_pg13 >;
227	pinctrl-names = "default";
228	phy-connection-type = "rmii";
229	phy-handle = <&eth_phy>;
230	status = "okay";
231};
232
233&mdio {
234	status = "okay";
235	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
236	pinctrl-names = "default";
237
238	eth_phy: ethernet-phy@0 {
239		compatible = "ethernet-phy";
240		reg = <0x00>;
241	};
242};
243
244sdhc: &sdmmc1 {
245	compatible = "st,stm32-sdio";
246	pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9
247			&sdmmc1_d2_pc10 &sdmmc1_d3_pc11
248			&sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>;
249	pinctrl-names = "default";
250	sdhi-on-gpios = <&gpioj 1 GPIO_ACTIVE_HIGH>;
251	interrupts = <49 0>;
252	interrupt-names = "event";
253	min-bus-freq = <DT_FREQ_K(400)>;
254	max-bus-freq = <DT_FREQ_M(208)>;
255	hw-flow-control;
256	bus-width = <4>;
257	status = "okay";
258
259	wifi: airoc-wifi {
260		status = "okay";
261		compatible = "infineon,airoc-wifi";
262		wifi-reg-on-gpios = <&gpioj 1 GPIO_ACTIVE_HIGH>;
263		wifi-host-wake-gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>;
264	};
265};
266
267zephyr_udc0: &usbotg_hs {
268	pinctrl-0 = < &usb_otg_hs_ulpi_d0_pa3
269		      &usb_otg_hs_ulpi_ck_pa5
270		      &usb_otg_hs_ulpi_d1_pb0
271		      &usb_otg_hs_ulpi_d2_pb1
272		      &usb_otg_hs_ulpi_d7_pb5
273		      &usb_otg_hs_ulpi_d3_pb10
274		      &usb_otg_hs_ulpi_d4_pb11
275		      &usb_otg_hs_ulpi_d5_pb12
276		      &usb_otg_hs_ulpi_d6_pb13
277		      &usb_otg_hs_ulpi_stp_pc0
278		      &usb_otg_hs_ulpi_nxt_ph4
279		      &usb_otg_hs_ulpi_dir_pi11 >;
280	pinctrl-names = "default";
281	phys = < &otghs_ulpi_phy >;
282	maximum-speed = "high-speed";
283	/* Include the USB1ULPIEN | USB1OTGHSULPIEN clock enable bit */
284	clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x6000000>,
285		 <&rcc STM32_SRC_HSI48 USB_SEL(3)>;
286	num-bidir-endpoints = < 4 >;
287	status = "okay";
288};
289