1/*
2 * Copyright (c) 2018-2019 Linaro Limited
3 * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8/dts-v1/;
9
10#include <mem.h>
11#include <arm/armv8-m.dtsi>
12#include <zephyr/dt-bindings/i2c/i2c.h>
13#include <zephyr/dt-bindings/input/input-event-codes.h>
14
15/ {
16	compatible = "arm,mps2";
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	aliases {
21		led0 = &led_0;
22		led1 = &led_1;
23		sw0 = &user_button_0;
24		sw1 = &user_button_1;
25		uart-1 = &uart1;
26		watchdog0 = &wdog0;
27	};
28
29	chosen {
30		zephyr,console = &uart0;
31		zephyr,shell-uart = &uart0;
32
33		/*
34		 * These SRAM and flash settings give the entire available
35		 * code and data memories to this secure firmware image.
36		 * This may conflict with mps2_an521_remote firmware. Use
37		 * caution when using both targets simultaneously.
38		 */
39		zephyr,sram = &ssram2_3;
40		zephyr,flash = &ssram1;
41	};
42
43	leds {
44		compatible = "gpio-leds";
45		led_0: led_0 {
46			gpios = <&gpio_led0 0>;
47			label = "USERLED0";
48		};
49		led_1: led_1 {
50			gpios = <&gpio_led0 1>;
51			label = "USERLED1";
52		};
53	};
54
55	gpio_keys {
56		compatible = "gpio-keys";
57		user_button_0: button_0 {
58			label = "USERPB0";
59			gpios = <&gpio_button 0>;
60			zephyr,code = <INPUT_KEY_0>;
61		};
62		user_button_1: button_1 {
63			label = "USERPB1";
64			gpios = <&gpio_button 1>;
65			zephyr,code = <INPUT_KEY_1>;
66		};
67	};
68
69	cpus {
70		#address-cells = <1>;
71		#size-cells = <0>;
72
73		cpu@0 {
74			device_type = "cpu";
75			compatible = "arm,cortex-m33";
76			reg = <0>;
77			#address-cells = <1>;
78			#size-cells = <1>;
79
80			mpu: mpu@e000ed90 {
81				compatible = "arm,armv8m-mpu";
82				reg = <0xe000ed90 0x40>;
83			};
84		};
85	};
86
87	/*
88	 * The memory regions defined below are according to AN521:
89	 * https://documentation-service.arm.com/static/5fa12fe9b1a7c5445f29017f
90	 *
91	 * Please see tables mentioned in individual comments below for details.
92	 */
93
94	ssram1: memory@10000000 {
95		/* Table 3-2, row 6. */
96		compatible = "zephyr,memory-region", "mmio-sram";
97		reg = <0x10000000 DT_SIZE_M(4)>;
98		zephyr,memory-region = "SSRAM1";
99	};
100
101	ssram2_3: memory@38000000 {
102		/* Table 3-4, rows 16 and 17. */
103		compatible = "zephyr,memory-region", "mmio-sram";
104		reg = <0x38000000 DT_SIZE_M(4)>;
105		zephyr,memory-region = "SSRAM2_3";
106	};
107
108	psram: memory@80000000 {
109		/* Table 3-6, row 1. */
110		device_type = "memory";
111		reg = <0x80000000 DT_SIZE_M(16)>;
112	};
113
114	soc {
115		peripheral@50000000 {
116			#address-cells = <1>;
117			#size-cells = <1>;
118			ranges = <0x0 0x50000000 0x10000000>;
119
120			#include "mps2_an521-common.dtsi"
121		};
122	};
123};
124
125&nvic {
126	arm,num-irq-priority-bits = <3>;
127};
128
129&uart1 {
130	status = "okay";
131};
132
133#include "mps2-pinctrl.dtsi"
134