1/*
2 * Copyright (c) 2018-2019 Linaro Limited
3 * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8/dts-v1/;
9
10#include <mem.h>
11#include <arm/armv8-m.dtsi>
12#include <zephyr/dt-bindings/i2c/i2c.h>
13#include <zephyr/dt-bindings/input/input-event-codes.h>
14
15/ {
16	compatible = "arm,mps2";
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	aliases {
21		led0 = &led_0;
22		led1 = &led_1;
23		sw0 = &user_button_0;
24		sw1 = &user_button_1;
25		watchdog0 = &wdog0;
26	};
27
28	chosen {
29		zephyr,console = &uart0;
30		zephyr,shell-uart = &uart0;
31		zephyr,sram = &ram;
32		zephyr,flash = &code;
33	};
34
35	leds {
36		compatible = "gpio-leds";
37		led_0: led_0 {
38			gpios = <&gpio_led0 0>;
39			label = "USERLED0";
40		};
41		led_1: led_1 {
42			gpios = <&gpio_led0 1>;
43			label = "USERLED1";
44		};
45	};
46
47	gpio_keys {
48		compatible = "gpio-keys";
49		user_button_0: button_0 {
50			label = "USERPB0";
51			gpios = <&gpio_button 0>;
52			zephyr,code = <INPUT_KEY_0>;
53		};
54		user_button_1: button_1 {
55			label = "USERPB1";
56			gpios = <&gpio_button 1>;
57			zephyr,code = <INPUT_KEY_1>;
58		};
59	};
60
61	cpus {
62		#address-cells = <1>;
63		#size-cells = <0>;
64
65		cpu@0 {
66			device_type = "cpu";
67			compatible = "arm,cortex-m33";
68			reg = <0>;
69			#address-cells = <1>;
70			#size-cells = <1>;
71
72			mpu: mpu@e000ed90 {
73				compatible = "arm,armv8m-mpu";
74				reg = <0xe000ed90 0x40>;
75			};
76		};
77	};
78
79	/*
80	 * The memory regions defined below are according to AN521:
81	 * https://documentation-service.arm.com/static/5fa12fe9b1a7c5445f29017f
82	 *
83	 * Please see tables mentioned in individual comments below for details.
84	 */
85
86	ssram1: memory@0 {
87		/* Table 3-2, row 1. */
88		compatible = "zephyr,memory-region", "mmio-sram";
89		reg = <0x0 DT_SIZE_M(4)>;
90		zephyr,memory-region = "SSRAM1";
91	};
92
93	ssram2_3: memory@28000000 {
94		/* Table 3-4, rows 8 and 9. */
95		compatible = "zephyr,memory-region", "mmio-sram";
96		reg = <0x28000000 DT_SIZE_M(4)>;
97		zephyr,memory-region = "SSRAM2_3";
98	};
99
100	psram: memory@80000000 {
101		/* Table 3-6, row 1. */
102		device_type = "memory";
103		reg = <0x80000000 DT_SIZE_M(16)>;
104	};
105
106	reserved-memory {
107		#address-cells = <1>;
108		#size-cells = <1>;
109		ranges;
110
111		/* The code memory region defined below is selected to remain
112		 * compatible with what TF-M has defined for a single boot image,
113		 * where 468 KB memory at the bottom of the 4 MB code region is
114		 * marked as 'Unused'. Please see the memory layout in:
115		 *
116		 * https://github.com/zephyrproject-rtos/trusted-firmware-m/blob/master/platform/ext/target/arm/mps2/an521/partition/flash_layout.h
117		 */
118
119		code: memory@38B000 {
120			reg = <0x0038B000 DT_SIZE_K(468)>;
121		};
122
123		/* This ram memory region's base address is chosen to avoid
124		 * conflict with the mps2_an521_ns board's RAM region.
125		 *
126		 * Its available address space must be compatible with what
127		 * TF-M assigns to NS firmware.
128		 */
129		ram: memory@28180000 {
130			reg = <0x28180000 DT_SIZE_K(512)>;
131		};
132	};
133
134	soc {
135		peripheral@40000000 {
136			#address-cells = <1>;
137			#size-cells = <1>;
138			ranges = <0x0 0x40000000 0x10000000>;
139
140			#include "mps2_an521-common.dtsi"
141		};
142	};
143};
144
145&nvic {
146	arm,num-irq-priority-bits = <3>;
147};
148
149#include "mps2-pinctrl.dtsi"
150