1/*
2 * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <arm/armv8.1-m.dtsi>
10#include <zephyr/dt-bindings/i2c/i2c.h>
11#include <zephyr/dt-bindings/input/input-event-codes.h>
12#include <mem.h>
13
14/ {
15	compatible = "arm,mps4-fvp";
16	#address-cells = <1>;
17	#size-cells = <1>;
18
19	chosen {
20		zephyr,console = &uart0;
21		zephyr,shell-uart = &uart0;
22		zephyr,sram = &ram;
23		zephyr,flash = &code;
24	};
25
26	cpus {
27		#address-cells = <1>;
28		#size-cells = <0>;
29
30		cpu@0 {
31			device_type = "cpu";
32			compatible = "arm,cortex-m85";
33			reg = <0>;
34			#address-cells = <1>;
35			#size-cells = <1>;
36
37			mpu: mpu@e000ed90 {
38				compatible = "arm,armv8.1m-mpu";
39				reg = <0xe000ed90 0x40>;
40			};
41		};
42	};
43
44	/* We utilize the non-secure addresses, if you add 0x10000000
45	 * you'll get the secure alias
46	 */
47	itcm: itcm@0 {
48		compatible = "zephyr,memory-region";
49		reg = <0x0 DT_SIZE_K(32)>;
50		zephyr,memory-region = "ITCM";
51	};
52
53	sram: sram@1000000 {
54		compatible = "zephyr,memory-region", "mmio-sram";
55		reg = <0x1000000 DT_SIZE_M(2)>;
56		zephyr,memory-region = "SRAM";
57	};
58
59	dtcm: dtcm@20000000 {
60		compatible = "zephyr,memory-region";
61		reg = <0x20000000 DT_SIZE_K(512)>;
62		zephyr,memory-region = "DTCM";
63	};
64
65	isram: sram@21000000 {
66		compatible = "zephyr,memory-region", "mmio-sram";
67		reg = <0x21000000 DT_SIZE_M(4)>;
68		zephyr,memory-region = "ISRAM";
69	};
70
71	reserved-memory {
72		#address-cells = <1>;
73		#size-cells = <1>;
74		ranges;
75
76		/* The memory regions defined below must match what the TF-M
77		 * project has defined for that board - a single image boot is
78		 * assumed. Please see the memory layout in:
79		 * https://git.trustedfirmware.org/plugins/gitiles/TF-M/trusted-firmware-m.git/+/HEAD/platform/ext/target/arm/mps4/common/partition/flash_layout.h
80		 */
81
82		code: memory@28080000 {
83			reg = <0x28080000 DT_SIZE_K(512)>;
84		};
85
86		ram: memory@21020000 {
87			reg = <0x21020000 DT_SIZE_M(1)>;
88		};
89	};
90
91	soc {
92		peripheral@40000000 {
93			#address-cells = <1>;
94			#size-cells = <1>;
95			ranges = <0x0 0x40000000 0x10000000>;
96
97			#include "mps4_common_soc_peripheral.dtsi"
98		};
99	};
100};
101
102#include "mps4_common.dtsi"
103