1# Copyright (c) 2022-2024 Intel Corporation 2# SPDX-License-Identifier: Apache-2.0 3 4 5config BUILD_OUTPUT_STRIPPED 6 default y 7 8config MP_MAX_NUM_CPUS 9 default 2 10 11if BOARD_INTEL_RPL_S_CRB 12 13# TSC on this board is 2.4 GHz for RPL-S, HPET and APIC are 19.2 MHz 14config SYS_CLOCK_HW_CYCLES_PER_SEC 15 default 2400000000 if APIC_TSC_DEADLINE_TIMER 16 default 2400000000 if APIC_TIMER_TSC 17 default 19200000 18 19endif #BOARD_INTEL_RPL_S_CRB 20 21if BOARD_INTEL_RPL_P_CRB 22 23# TSC on this board is 1.8 GHz for RPL-P, HPET and APIC are 19.2 MHz 24config SYS_CLOCK_HW_CYCLES_PER_SEC 25 default 1800000000 if APIC_TSC_DEADLINE_TIMER 26 default 1800000000 if APIC_TIMER_TSC 27 default 19200000 28 29endif #BOARD_INTEL_RPL_P_CRB 30 31if APIC_TIMER 32config APIC_TIMER_IRQ 33 default 24 34endif 35if APIC_TIMER_TSC 36config APIC_TIMER_TSC_M 37 default 3 38config APIC_TIMER_TSC_N 39 default 249 40endif 41 42config ACPI 43 default y 44 45if ACPI 46config HEAP_MEM_POOL_ADD_SIZE_ACPI 47 default 64000000 48config MAIN_STACK_SIZE 49 default 320000 50 51if SHELL 52config SHELL_STACK_SIZE 53 default 320000 54endif # SHELL 55endif # ACPI 56 57if DMA 58config DMA_64BIT 59 default y 60config DMA_DW_HW_LLI 61 default n 62config DMA_DW_CHANNEL_COUNT 63 default 2 64endif 65 66config UART_NS16550_INTEL_LPSS_DMA 67 default y if BOARD_INTEL_RPL_S_CRB 68 69if SHELL 70config SHELL_STACK_SIZE 71 default 320000 72endif 73 74config HAS_COVERAGE_SUPPORT 75 default y 76