1 /* 2 * Copyright (c) 2017 Oticon A/S 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 /** 7 * @file Extra definitions provided by the board to soc.h 8 * 9 * Background: 10 * The POSIX ARCH/SOC/board layering is different than in normal archs 11 * The "SOC" does not provide almost any of the typical SOC functionality 12 * but that is left for the "board" to define it 13 * Device code may rely on the soc.h defining some things (like the interrupts 14 * numbers) 15 * Therefore this file is included from the inf_clock soc.h to allow a board 16 * to define that kind of SOC related snippets 17 */ 18 19 #ifndef BOARDS_POSIX_NRF_BSIM_BOARD_SOC_H 20 #define BOARDS_POSIX_NRF_BSIM_BOARD_SOC_H 21 22 #include <zephyr/toolchain.h> 23 #include <zephyr/sys/util.h> 24 25 #include <stdint.h> 26 #include <stdbool.h> 27 #include <zephyr/types.h> 28 #include <stddef.h> 29 #include <zephyr/irq.h> 30 #include <nrfx.h> 31 #include "cmsis.h" 32 #include "soc_nrf_common.h" 33 34 /* For offloading interrupts we can use any free interrupt */ 35 #if defined(CONFIG_BOARD_NRF52_BSIM) 36 #define OFFLOAD_SW_IRQ SWI0_EGU0_IRQn 37 #elif defined(CONFIG_BOARD_NRF5340BSIM_NRF5340_CPUAPP) 38 #define OFFLOAD_SW_IRQ EGU0_IRQn 39 #elif defined(CONFIG_BOARD_NRF5340BSIM_NRF5340_CPUNET) 40 #define OFFLOAD_SW_IRQ SWI0_IRQn 41 #elif defined(CONFIG_SOC_SERIES_BSIM_NRF54LX) 42 #define OFFLOAD_SW_IRQ SWI00_IRQn 43 #endif 44 45 #define FLASH_PAGE_ERASE_MAX_TIME_US 89700UL 46 #define FLASH_PAGE_MAX_CNT 256UL 47 48 #ifdef __cplusplus 49 extern "C" { 50 #endif 51 52 #ifdef __cplusplus 53 } 54 #endif 55 56 #endif /* BOARDS_POSIX_NRF_BSIM_BOARD_SOC_H */ 57