1/* 2 * Copyright 2025 NXP 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 7#include <nxp/mcx/MCXA266VLQ-pinctrl.h> 8 9&pinctrl { 10 pinmux_lpuart2: pinmux_lpuart2 { 11 group0 { 12 pinmux = <LPUART2_RXD_P2_3>, 13 <LPUART2_TXD_P2_2>; 14 drive-strength = "low"; 15 slew-rate = "fast"; 16 input-enable; 17 }; 18 }; 19 20 pinmux_lpuart3: pinmux_lpuart3 { 21 group0 { 22 pinmux = <LPUART3_RXD_P4_2>, 23 <LPUART3_TXD_P4_5>; 24 drive-strength = "low"; 25 slew-rate = "fast"; 26 input-enable; 27 }; 28 }; 29 30 pinmux_i3c0: pinmux_i3c0 { 31 group0 { 32 pinmux = <I3C0_SDA_P1_8>, 33 <I3C0_SCL_P1_9>; 34 slew-rate = "fast"; 35 drive-strength = "low"; 36 input-enable; 37 bias-pull-up; 38 }; 39 group1 { 40 pinmux = <I3C0_PUR_P0_2>; 41 slew-rate = "fast"; 42 drive-strength = "low"; 43 input-enable; 44 }; 45 }; 46 pinmux_lpadc0: pinmux_lpadc0 { 47 group0 { 48 pinmux = <ADC0_A7_P2_7>; 49 slew-rate = "fast"; 50 drive-strength = "low"; 51 }; 52 }; 53 pinmux_lpcmp0: pinmux_lpcmp0 { 54 group0 { 55 pinmux = <CMP0_IN1_P1_3>; 56 drive-strength = "low"; 57 slew-rate = "fast"; 58 bias-pull-up; 59 }; 60 }; 61 pinmux_lpi2c1: pinmux_lpi2c1 { 62 group0 { 63 pinmux = <LPI2C1_SDA_P1_0>, 64 <LPI2C1_SCL_P1_1>; 65 slew-rate = "fast"; 66 drive-strength = "low"; 67 input-enable; 68 bias-pull-up; 69 drive-open-drain; 70 }; 71 }; 72 pinmux_lpi2c2: pinmux_lpi2c2 { 73 group0 { 74 pinmux = <LPI2C2_SDA_P1_8>, 75 <LPI2C2_SCL_P1_9>; 76 slew-rate = "fast"; 77 drive-strength = "low"; 78 input-enable; 79 bias-pull-up; 80 drive-open-drain; 81 }; 82 }; 83 pinmux_lpi2c3: pinmux_lpi2c3 { 84 group0 { 85 pinmux = <LPI2C3_SDA_P3_28>, 86 <LPI2C3_SCL_P3_27>; 87 slew-rate = "fast"; 88 drive-strength = "low"; 89 input-enable; 90 bias-pull-up; 91 drive-open-drain; 92 }; 93 }; 94 95 pinmux_lpspi0: pinmux_lpspi0 { 96 group0 { 97 pinmux = <LPSPI0_SDO_P1_0>, 98 <LPSPI0_SCK_P1_1>, 99 <LPSPI0_SDI_P1_2>, 100 <LPSPI0_PCS0_P1_3>; 101 slew-rate = "fast"; 102 drive-strength = "low"; 103 input-enable; 104 }; 105 }; 106}; 107