1 /* 2 * Copyright 2018-2020 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 #ifndef __EVKMIMXRT1015_FLEXSPI_NOR_CONFIG__ 9 #define __EVKMIMXRT1015_FLEXSPI_NOR_CONFIG__ 10 11 #include <stdint.h> 12 #include <stdbool.h> 13 #include "fsl_common.h" 14 15 /*! @name Driver version */ 16 /*@{*/ 17 /*! @brief XIP_BOARD driver version 2.0.1. */ 18 #define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) 19 /*@}*/ 20 21 /* FLEXSPI memory config block related definitions */ 22 #define FLEXSPI_CFG_BLK_TAG (0x42464346UL) /* ascii "FCFB" Big Endian */ 23 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) /* V1.4.0 */ 24 #define FLEXSPI_CFG_BLK_SIZE (512) 25 26 /* FLEXSPI Feature related definitions */ 27 #define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 28 29 /* Lookup table related definitions */ 30 #define CMD_INDEX_READ 0 31 #define CMD_INDEX_READSTATUS 1 32 #define CMD_INDEX_WRITEENABLE 2 33 #define CMD_INDEX_WRITE 4 34 35 #define CMD_LUT_SEQ_IDX_READ 0 36 #define CMD_LUT_SEQ_IDX_READSTATUS 1 37 #define CMD_LUT_SEQ_IDX_WRITEENABLE 3 38 #define CMD_LUT_SEQ_IDX_WRITE 9 39 40 #define CMD_SDR 0x01 41 #define CMD_DDR 0x21 42 #define RADDR_SDR 0x02 43 #define RADDR_DDR 0x22 44 #define CADDR_SDR 0x03 45 #define CADDR_DDR 0x23 46 #define MODE1_SDR 0x04 47 #define MODE1_DDR 0x24 48 #define MODE2_SDR 0x05 49 #define MODE2_DDR 0x25 50 #define MODE4_SDR 0x06 51 #define MODE4_DDR 0x26 52 #define MODE8_SDR 0x07 53 #define MODE8_DDR 0x27 54 #define WRITE_SDR 0x08 55 #define WRITE_DDR 0x28 56 #define READ_SDR 0x09 57 #define READ_DDR 0x29 58 #define LEARN_SDR 0x0A 59 #define LEARN_DDR 0x2A 60 #define DATSZ_SDR 0x0B 61 #define DATSZ_DDR 0x2B 62 #define DUMMY_SDR 0x0C 63 #define DUMMY_DDR 0x2C 64 #define DUMMY_RWDS_SDR 0x0D 65 #define DUMMY_RWDS_DDR 0x2D 66 #define JMP_ON_CS 0x1F 67 #define STOP 0 68 69 #define FLEXSPI_1PAD 0 70 #define FLEXSPI_2PAD 1 71 #define FLEXSPI_4PAD 2 72 #define FLEXSPI_8PAD 3 73 74 #define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ 75 (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | \ 76 FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ 77 FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) 78 79 /*! @brief Definitions for FlexSPI Serial Clock Frequency */ 80 typedef enum _FlexSpiSerialClockFreq { 81 kFlexSpiSerialClk_30MHz = 1, 82 kFlexSpiSerialClk_50MHz = 2, 83 kFlexSpiSerialClk_60MHz = 3, 84 kFlexSpiSerialClk_75MHz = 4, 85 kFlexSpiSerialClk_80MHz = 5, 86 kFlexSpiSerialClk_100MHz = 6, 87 kFlexSpiSerialClk_133MHz = 7, 88 } flexspi_serial_clk_freq_t; 89 90 /*! @brief FlexSPI clock configuration type */ 91 enum { 92 /* Clock configure for SDR mode */ 93 kFlexSpiClk_SDR, 94 /* Clock configurat for DDR mode */ 95 kFlexSpiClk_DDR, 96 }; 97 98 /*! @brief FlexSPI Read Sample Clock Source definition */ 99 typedef enum _FlashReadSampleClkSource { 100 kFlexSPIReadSampleClk_LoopbackInternally = 0, 101 kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, 102 kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, 103 kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, 104 } flexspi_read_sample_clk_t; 105 106 /*! @brief Misc feature bit definitions */ 107 enum { 108 /* Bit for Differential clock enable */ 109 kFlexSpiMiscOffset_DiffClkEnable = 0, 110 /* Bit for CK2 enable */ 111 kFlexSpiMiscOffset_Ck2Enable = 1, 112 /* Bit for Parallel mode enable */ 113 kFlexSpiMiscOffset_ParallelEnable = 2, 114 /* Bit for Word Addressable enable */ 115 kFlexSpiMiscOffset_WordAddressableEnable = 3, 116 /* Bit for Safe Configuration Frequency enable */ 117 kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, 118 /* Bit for Pad setting override enable */ 119 kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, 120 /* Bit for DDR clock confiuration indication. */ 121 kFlexSpiMiscOffset_DdrModeEnable = 6, 122 }; 123 124 /*! @brief Flash Type Definition */ 125 enum { 126 /* Flash devices are Serial NOR */ 127 kFlexSpiDeviceType_SerialNOR = 1, 128 /* Flash devices are Serial NAND */ 129 kFlexSpiDeviceType_SerialNAND = 2, 130 /* Flash devices are Serial RAM/HyperFLASH */ 131 kFlexSpiDeviceType_SerialRAM = 3, 132 /* Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND */ 133 kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, 134 /* Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs */ 135 kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, 136 }; 137 138 /*! @brief Flash Pad Definitions */ 139 enum { 140 kSerialFlash_1Pad = 1, 141 kSerialFlash_2Pads = 2, 142 kSerialFlash_4Pads = 4, 143 kSerialFlash_8Pads = 8, 144 }; 145 146 /*! @brief FlexSPI LUT Sequence structure */ 147 typedef struct _lut_sequence { 148 uint8_t seqNum; /* Sequence Number, valid number: 1-16 */ 149 uint8_t seqId; /* Sequence Index, valid number: 0-15 */ 150 uint16_t reserved; 151 } flexspi_lut_seq_t; 152 153 /*! @brief Flash Configuration Command Type */ 154 enum { 155 /* Generic command, for example: configure dummy cycles, 156 * drive strength, etc 157 */ 158 kDeviceConfigCmdType_Generic, 159 /* Quad Enable command */ 160 kDeviceConfigCmdType_QuadEnable, 161 /* Switch from SPI to DPI/QPI/OPI mode */ 162 kDeviceConfigCmdType_Spi2Xpi, 163 /* Switch from DPI/QPI/OPI to SPI mode */ 164 kDeviceConfigCmdType_Xpi2Spi, 165 /* Switch to 0-4-4/0-8-8 mode */ 166 kDeviceConfigCmdType_Spi2NoCmd, 167 /* Reset device command */ 168 kDeviceConfigCmdType_Reset, 169 }; 170 171 /*! @brief FlexSPI Memory Configuration Block */ 172 typedef struct _FlexSPIConfig { 173 /* [0x000-0x003] Tag, fixed value 0x42464346UL */ 174 uint32_t tag; 175 /* [0x004-0x007] Version, [31:24] -'V', 176 * [23:16] - Major, 177 * [15:8] - Minor, 178 * [7:0] - bugfix 179 */ 180 uint32_t version; 181 /* [0x008-0x00b] Reserved for future use */ 182 uint32_t reserved0; 183 /* [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 */ 184 uint8_t readSampleClkSrc; 185 /* [0x00d-0x00d] CS hold time, default value: 3 */ 186 uint8_t csHoldTime; 187 /* [0x00e-0x00e] CS setup time, default value: 3 */ 188 uint8_t csSetupTime; 189 /* [0x00f-0x00f] Column Address with, for HyperBus protocol, 190 * it is fixed to 3, For Serial NAND, need to refer to datasheet 191 */ 192 uint8_t columnAddressWidth; 193 /* [0x010-0x010] Device Mode Configure enable flag, 194 * 1 - Enable, 0 - Disable 195 */ 196 uint8_t deviceModeCfgEnable; 197 /* [0x011-0x011] Specify the configuration command type:Quad Enable, 198 * DPI/QPI/OPI switch, Generic configuration, etc. 199 */ 200 uint8_t deviceModeType; 201 /* [0x012-0x013] Wait time for all configuration commands, 202 * unit: 100us, Used for DPI/QPI/OPI switch or reset command 203 */ 204 uint16_t waitTimeCfgCommands; 205 /* [0x014-0x017] Device mode sequence info, 206 * [7:0] - LUT sequence id, 207 * [15:8] - LUt sequence number, 208 * [31:16] Reserved 209 */ 210 flexspi_lut_seq_t deviceModeSeq; 211 /* [0x018-0x01b] Argument/Parameter for device configuration */ 212 uint32_t deviceModeArg; 213 /* [0x01c-0x01c] Configure command Enable Flag, 214 * 1 - Enable, 0 - Disable 215 */ 216 uint8_t configCmdEnable; 217 /* [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe */ 218 uint8_t configModeType[3]; 219 /* [0x020-0x02b] Sequence info for Device Configuration command, 220 * similar as deviceModeSeq 221 */ 222 flexspi_lut_seq_t configCmdSeqs[3]; 223 /* [0x02c-0x02f] Reserved for future use */ 224 uint32_t reserved1; 225 /* [0x030-0x03b] Arguments/Parameters for 226 * device Configuration commands 227 */ 228 uint32_t configCmdArgs[3]; 229 /* [0x03c-0x03f] Reserved for future use */ 230 uint32_t reserved2; 231 /* [0x040-0x043] Controller Misc Options, see Misc feature bit 232 * definitions for more details 233 */ 234 uint32_t controllerMiscOption; 235 /* [0x044-0x044] Device Type: 236 * See Flash Type Definition for more details 237 */ 238 uint8_t deviceType; 239 /* [0x045-0x045] Serial Flash Pad Type: 240 * 1 - Single, 241 * 2 - Dual, 242 * 4 - Quad, 243 * 8 - Octal 244 */ 245 uint8_t sflashPadType; 246 /* [0x046-0x046] Serial Flash Frequencey, device specific 247 * definitions, See System Boot Chapter for more details 248 */ 249 uint8_t serialClkFreq; 250 /* [0x047-0x047] LUT customization Enable, it is required if 251 * the program/erase cannot be done using 1 LUT sequence, 252 * currently, only applicable to HyperFLASH 253 */ 254 uint8_t lutCustomSeqEnable; 255 /* [0x048-0x04f] Reserved for future use */ 256 uint32_t reserved3[2]; 257 /* [0x050-0x053] Size of Flash connected to A1 */ 258 uint32_t sflashA1Size; 259 /* [0x054-0x057] Size of Flash connected to A2 */ 260 uint32_t sflashA2Size; 261 /* [0x058-0x05b] Size of Flash connected to B1 */ 262 uint32_t sflashB1Size; 263 /* [0x05c-0x05f] Size of Flash connected to B2 */ 264 uint32_t sflashB2Size; 265 /* [0x060-0x063] CS pad setting override value */ 266 uint32_t csPadSettingOverride; 267 /* [0x064-0x067] SCK pad setting override value */ 268 uint32_t sclkPadSettingOverride; 269 /* [0x068-0x06b] data pad setting override value */ 270 uint32_t dataPadSettingOverride; 271 /* [0x06c-0x06f] DQS pad setting override value */ 272 uint32_t dqsPadSettingOverride; 273 /* [0x070-0x073] Timeout threshold for read status command */ 274 uint32_t timeoutInMs; 275 /* [0x074-0x077] CS deselect interval between two commands */ 276 uint32_t commandInterval; 277 /* [0x078-0x07b] CLK edge to data valid time 278 * for PORT A and PORT B, in terms of 0.1ns 279 */ 280 uint16_t dataValidTime[2]; 281 /* [0x07c-0x07d] Busy offset, valid value: 0-31 */ 282 uint16_t busyOffset; 283 /* [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 284 * when flash device is busy, 1 - busy flag is 0 when 285 * flash device is busy 286 */ 287 uint16_t busyBitPolarity; 288 /* [0x080-0x17f] Lookup table holds Flash command sequences */ 289 uint32_t lookupTable[64]; 290 /* [0x180-0x1af] Customizable LUT Sequences */ 291 flexspi_lut_seq_t lutCustomSeq[12]; 292 /* [0x1b0-0x1bf] Reserved for future use */ 293 uint32_t reserved4[4]; 294 } flexspi_mem_config_t; 295 296 #define NOR_CMD_INDEX_READ CMD_INDEX_READ /* 0 */ 297 #define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS /* 1 */ 298 #define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE /* 2 */ 299 #define NOR_CMD_INDEX_ERASESECTOR 3 /* 3 */ 300 #define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE /* 4 */ 301 #define NOR_CMD_INDEX_CHIPERASE 5 /* 5 */ 302 #define NOR_CMD_INDEX_DUMMY 6 /* 6 */ 303 #define NOR_CMD_INDEX_ERASEBLOCK 7 /* 7 */ 304 305 /* 0 READ LUT sequence id in lookupTable stored in config block */ 306 #define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ 307 /* 1 Read Status LUT sequence id in lookupTable stored in config block */ 308 #define NOR_CMD_LUT_SEQ_IDX_READSTATUS CMD_LUT_SEQ_IDX_READSTATUS 309 /* 2 Read status DPI/QPI/OPI sequence id in 310 * lookupTable stored in config block 311 */ 312 #define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 2 313 /* 3 Write Enable sequence id in lookupTable stored in config block */ 314 #define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE CMD_LUT_SEQ_IDX_WRITEENABLE 315 /* 4 Write Enable DPI/QPI/OPI sequence id in 316 * lookupTable stored in config block 317 */ 318 #define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI 4 319 /* 5 Erase Sector sequence id in lookupTable stored in config block */ 320 #define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 321 /* 8 Erase Block sequence id in lookupTable stored in config block */ 322 #define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 323 /* 9 Program sequence id in lookupTable stored in config block */ 324 #define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM CMD_LUT_SEQ_IDX_WRITE 325 /* 11 Chip Erase sequence in lookupTable id stored in config block */ 326 #define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 327 /* 13 Read SFDP sequence in lookupTable id stored in config block */ 328 #define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 329 /* 14 Restore 0-4-4/0-8-8 mode sequence id in 330 * lookupTable stored in config block 331 */ 332 #define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD 14 333 /* 15 Exit 0-4-4/0-8-8 mode sequence id in 334 * lookupTable stored in config blobk 335 */ 336 #define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD 15 337 338 /* 339 * Serial NOR configuration block 340 */ 341 typedef struct _flexspi_nor_config { 342 /* Common memory configuration info via FlexSPI */ 343 flexspi_mem_config_t memConfig; 344 /* Page size of Serial NOR */ 345 uint32_t pageSize; 346 /* Sector size of Serial NOR */ 347 uint32_t sectorSize; 348 /* Clock frequency for IP command */ 349 uint8_t ipcmdSerialClkFreq; 350 /* Sector/Block size is the same */ 351 uint8_t isUniformBlockSize; 352 /* Reserved for future use */ 353 uint8_t reserved0[2]; 354 /* Serial NOR Flash type: 0/1/2/3 */ 355 uint8_t serialNorType; 356 /* Need to exit NoCmd mode before other IP command */ 357 uint8_t needExitNoCmdMode; 358 /* Half the Serial Clock for non-read command: true/false */ 359 uint8_t halfClkForNonReadCmd; 360 /* Need to Restore NoCmd mode after IP commmand execution */ 361 uint8_t needRestoreNoCmdMode; 362 /* Block size */ 363 uint32_t blockSize; 364 /* Reserved for future use */ 365 uint32_t reserve2[11]; 366 } flexspi_nor_config_t; 367 368 #ifdef __cplusplus 369 extern "C" { 370 #endif 371 372 #ifdef __cplusplus 373 } 374 #endif 375 #endif /* #ifndef __EVKMIMXRT1015_FLEXSPI_NOR_CONFIG__ */ 376