1 /* 2 * Copyright 2018-2020 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 #include "evkmimxrt1170_flexspi_nor_config.h" 9 10 /* Component ID definition, used by tools. */ 11 #ifndef FSL_COMPONENT_ID 12 #define FSL_COMPONENT_ID "platform.drivers.xip_board" 13 #endif 14 15 #if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) 16 #if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) 17 __attribute__((section(".boot_hdr.conf"), used)) 18 #elif defined(__ICCARM__) 19 #pragma location = ".boot_hdr.conf" 20 #endif 21 22 #define FLASH_DUMMY_CYCLES 0x09 23 #define FLASH_DUMMY_VALUE 0x09 24 25 const flexspi_nor_config_t qspiflash_config = { 26 .memConfig = { 27 .tag = FLEXSPI_CFG_BLK_TAG, 28 .version = FLEXSPI_CFG_BLK_VERSION, 29 .readSampleClkSrc = 30 kFlexSPIReadSampleClk_LoopbackFromDqsPad, 31 .csHoldTime = 3u, 32 .csSetupTime = 3u, 33 /* Enable DDR mode, Wordaddassable, Safe configuration, Differential clock */ 34 .controllerMiscOption = 0x10, 35 .deviceType = kFlexSpiDeviceType_SerialNOR, 36 .sflashPadType = kSerialFlash_4Pads, 37 .serialClkFreq = kFlexSpiSerialClk_133MHz, 38 .sflashA1Size = 16u * 1024u * 1024u, 39 /* Enable flash configuration feature */ 40 .configCmdEnable = 1u, 41 .configModeType[0] = kDeviceConfigCmdType_Generic, 42 /* Set configuration command sequences */ 43 .configCmdSeqs[0] = { 44 .seqNum = 1, 45 .seqId = 12, 46 .reserved = 0, 47 }, 48 /* Prepare setting value for Read Register in flash */ 49 .configCmdArgs[0] = (FLASH_DUMMY_VALUE << 3), 50 .lookupTable = { 51 /* Read LUTs */ 52 [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 53 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), 54 [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 55 FLASH_DUMMY_CYCLES, READ_SDR, FLEXSPI_4PAD, 56 0x04), 57 58 /* Read Status LUTs */ 59 [4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 60 0x05, READ_SDR, FLEXSPI_1PAD, 0x04), 61 62 /* Write Enable LUTs */ 63 [4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 64 0x06, STOP, FLEXSPI_1PAD, 0x0), 65 66 /* Erase Sector LUTs */ 67 [4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 68 0x20, RADDR_SDR, FLEXSPI_1PAD, 0x18), 69 70 /* Erase Block LUTs */ 71 [4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 72 0xD8, RADDR_SDR, FLEXSPI_1PAD, 0x18), 73 74 /* Pape Program LUTs */ 75 [4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 76 0x02, RADDR_SDR, FLEXSPI_1PAD, 0x18), 77 [4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 78 0x04, STOP, FLEXSPI_1PAD, 0x0), 79 80 /* Erase Chip LUTs */ 81 [4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 82 0x60, STOP, FLEXSPI_1PAD, 0x0), 83 84 /* Set Read Register LUTs */ 85 [4 * 12 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 86 0xC0, WRITE_SDR, FLEXSPI_1PAD, 0x01), 87 [4 * 12 + 1] = FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 88 0x00, 0, 0, 0), 89 }, 90 }, 91 .pageSize = 256u, 92 .sectorSize = 4u * 1024u, 93 .ipcmdSerialClkFreq = 0x1, 94 .blockSize = 64u * 1024u, 95 .isUniformBlockSize = false, 96 }; 97 98 #endif /* XIP_BOOT_HEADER_ENABLE */ 99