1 /* 2 * Copyright 2018-2024 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 #ifndef __EVKMIMXRT1180_FLEXSPI_NOR_CONFIG__ 9 #define __EVKMIMXRT1180_FLEXSPI_NOR_CONFIG__ 10 11 #include "fsl_common.h" 12 13 /*! @name Driver version */ 14 /*@{*/ 15 /*! @brief XIP_DEVICE driver version 2.0.4. */ 16 #define FSL_XIP_DEVICE_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) 17 /*@}*/ 18 19 #define FLEXSPI_CFG_BLK_TAG (0x42464346UL) /* ascii "FCFB" Big Endian */ 20 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) /* V1.4.0 */ 21 22 #define CMD_SDR 0x01 23 #define CMD_DDR 0x21 24 #define RADDR_SDR 0x02 25 #define RADDR_DDR 0x22 26 #define CADDR_SDR 0x03 27 #define CADDR_DDR 0x23 28 #define MODE1_SDR 0x04 29 #define MODE1_DDR 0x24 30 #define MODE2_SDR 0x05 31 #define MODE2_DDR 0x25 32 #define MODE4_SDR 0x06 33 #define MODE4_DDR 0x26 34 #define MODE8_SDR 0x07 35 #define MODE8_DDR 0x27 36 #define WRITE_SDR 0x08 37 #define WRITE_DDR 0x28 38 #define READ_SDR 0x09 39 #define READ_DDR 0x29 40 #define LEARN_SDR 0x0A 41 #define LEARN_DDR 0x2A 42 #define DATSZ_SDR 0x0B 43 #define DATSZ_DDR 0x2B 44 #define DUMMY_SDR 0x0C 45 #define DUMMY_DDR 0x2C 46 #define DUMMY_RWDS_SDR 0x0D 47 #define DUMMY_RWDS_DDR 0x2D 48 #define JMP_ON_CS 0x1F 49 #define STOP 0 50 51 #define FLEXSPI_1PAD 0 52 #define FLEXSPI_2PAD 1 53 #define FLEXSPI_4PAD 2 54 #define FLEXSPI_8PAD 3 55 56 #define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ 57 (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | \ 58 FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ 59 FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) 60 61 /*! @brief FlexSPI Read Sample Clock Source definition */ 62 typedef enum _FlashReadSampleClkSource { 63 kFlexSPIReadSampleClk_LoopbackInternally = 0, 64 kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, 65 kFlexSPIReadSampleClk_Reversed = 2, 66 kFlexSPIReadSampleClk_FlashProvidedDqs = 3, 67 } flexspi_read_sample_clk_t; 68 69 /*! @brief Flash Type Definition */ 70 enum { 71 /* Flash devices are Serial NOR */ 72 kFlexSpiDeviceType_SerialNOR = 1, 73 /* Flash devices are Serial NAND */ 74 kFlexSpiDeviceType_SerialNAND = 2, 75 /* Flash devices are Serial RAM/HyperFLASH */ 76 kFlexSpiDeviceType_SerialRAM = 3 77 }; 78 79 /*! @brief Flash Pad Definitions */ 80 enum { 81 kSerialFlash_1Pad = 1, 82 kSerialFlash_2Pads = 2, 83 kSerialFlash_4Pads = 4, 84 kSerialFlash_8Pads = 8, 85 }; 86 87 /*! @brief Definitions for FlexSPI Serial Clock Frequency */ 88 typedef enum _FlexSpiSerialClockFreq { 89 kFlexSpiSerialClk_30MHz = 1, 90 kFlexSpiSerialClk_50MHz = 2, 91 kFlexSpiSerialClk_60MHz = 3, 92 kFlexSpiSerialClk_80MHz = 4, 93 kFlexSpiSerialClk_100MHz = 5, 94 kFlexSpiSerialClk_120MHz = 6, 95 kFlexSpiSerialClk_133MHz = 7, 96 kFlexSpiSerialClk_166MHz = 8, 97 } flexspi_serial_clk_freq_t; 98 99 /*! @brief Flash Configuration Command Type */ 100 enum { 101 /* Generic command, for example: configure dummy cycles, 102 * drive strength, etc 103 */ 104 kDeviceConfigCmdType_Generic, 105 /* Quad Enable command */ 106 kDeviceConfigCmdType_QuadEnable, 107 /* Switch from SPI to DPI/QPI/OPI mode */ 108 kDeviceConfigCmdType_Spi2Xpi, 109 /* Switch from DPI/QPI/OPI to SPI mode */ 110 kDeviceConfigCmdType_Xpi2Spi, 111 /* Switch to 0-4-4/0-8-8 mode */ 112 kDeviceConfigCmdType_Spi2NoCmd, 113 /* Reset device command */ 114 kDeviceConfigCmdType_Reset, 115 }; 116 117 /*! @brief FlexSPI LUT Sequence structure */ 118 typedef struct _lut_sequence { 119 uint8_t seqNum; /* Sequence Number, valid number: 1-16 */ 120 uint8_t seqId; /* Sequence Index, valid number: 0-15 */ 121 uint16_t reserved; 122 } flexspi_lut_seq_t; 123 124 /*! @brief FlexSPI Memory Configuration Block */ 125 typedef struct _FlexSPIConfig { 126 /* [0x000-0x003] Tag, fixed value 0x42464346UL */ 127 uint32_t tag; 128 /* [0x004-0x007] Version, [31:24] -'V', 129 * [23:16] - Major, 130 * [15:8] - Minor, 131 * [7:0] - bugfix 132 */ 133 uint32_t version; 134 /* [0x008-0x00b] Reserved for future use */ 135 uint32_t reserved0; 136 /* [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 */ 137 uint8_t readSampleClkSrc; 138 /* [0x00d-0x00d] CS hold time, default value: 3 */ 139 uint8_t csHoldTime; 140 /* [0x00e-0x00e] CS setup time, default value: 3 */ 141 uint8_t csSetupTime; 142 /* [0x00f-0x00f] Column Address with, for HyperBus protocol, 143 * it is fixed to 3, For Serial NAND, need to refer to datasheet 144 */ 145 uint8_t columnAddressWidth; 146 /* [0x010-0x010] Device Mode Configure enable flag, 147 * 1 - Enable, 0 - Disable 148 */ 149 uint8_t deviceModeCfgEnable; 150 /* [0x011-0x011] Specify the configuration command type:Quad Enable, 151 * DPI/QPI/OPI switch, Generic configuration, etc. 152 */ 153 uint8_t deviceModeType; 154 /* [0x012-0x013] Wait time for all configuration commands, 155 * unit: 100us, Used for DPI/QPI/OPI switch or reset command 156 */ 157 uint16_t waitTimeCfgCommands; 158 /* [0x014-0x017] Device mode sequence info, 159 * [7:0] - LUT sequence id, 160 * [15:8] - LUt sequence number, 161 * [31:16] Reserved 162 */ 163 flexspi_lut_seq_t deviceModeSeq; 164 /* [0x018-0x01b] Argument/Parameter for device configuration */ 165 uint32_t deviceModeArg; 166 /* [0x01c-0x01c] Configure command Enable Flag, 167 * 1 - Enable, 0 - Disable 168 */ 169 uint8_t configCmdEnable; 170 /* [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe */ 171 uint8_t configModeType[3]; 172 /* [0x020-0x02b] Sequence info for Device Configuration command, 173 * similar as deviceModeSeq 174 */ 175 flexspi_lut_seq_t configCmdSeqs[3]; 176 /* [0x02c-0x02f] Reserved for future use */ 177 uint32_t reserved1; 178 /* [0x030-0x03b] Arguments/Parameters 179 * for device Configuration commands 180 */ 181 uint32_t configCmdArgs[3]; 182 /* [0x03c-0x03f] Reserved for future use */ 183 uint32_t reserved2; 184 /* [0x040-0x043] Controller Misc Options, see Misc feature bit 185 * definitions for more details 186 */ 187 uint32_t controllerMiscOption; 188 /* [0x044-0x044] Device Type: See Flash Type Definition 189 * for more details 190 */ 191 uint8_t deviceType; 192 /* [0x045-0x045] Serial Flash Pad Type: 193 * 1 - Single, 194 * 2 - Dual, 195 * 4 - Quad, 196 * 8 - Octal 197 */ 198 uint8_t sflashPadType; 199 /* [0x046-0x046] Serial Flash Frequencey, device specific 200 * definitions, See System Boot Chapter for more details 201 */ 202 uint8_t serialClkFreq; 203 /* [0x047-0x047] LUT customization Enable, it is required if 204 * the program/erase cannot be done using 1 LUT sequence, 205 * currently, only applicable to HyperFLASH 206 */ 207 uint8_t lutCustomSeqEnable; 208 /* [0x048-0x04f] Reserved for future use */ 209 uint32_t reserved3[2]; 210 /* [0x050-0x053] Size of Flash connected to A1 */ 211 uint32_t sflashA1Size; 212 /* [0x054-0x057] Size of Flash connected to A2 */ 213 uint32_t sflashA2Size; 214 /* [0x058-0x05b] Size of Flash connected to B1 */ 215 uint32_t sflashB1Size; 216 /* [0x05c-0x05f] Size of Flash connected to B2 */ 217 uint32_t sflashB2Size; 218 /* [0x060-0x063] CS pad setting override value */ 219 uint32_t csPadSettingOverride; 220 /* [0x064-0x067] SCK pad setting override value */ 221 uint32_t sclkPadSettingOverride; 222 /* [0x068-0x06b] data pad setting override value */ 223 uint32_t dataPadSettingOverride; 224 /* [0x06c-0x06f] DQS pad setting override value */ 225 uint32_t dqsPadSettingOverride; 226 /* [0x070-0x073] Timeout threshold for read status command */ 227 uint32_t timeoutInMs; 228 /* [0x074-0x077] CS deselect interval between two commands */ 229 uint32_t commandInterval; 230 /* [0x078-0x07b] CLK edge to data valid time 231 * for PORT A and PORT B, in terms of 0.1ns 232 */ 233 uint16_t dataValidTime[2]; 234 /* [0x07c-0x07d] Busy offset, valid value: 0-31 */ 235 uint16_t busyOffset; 236 /* [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 237 * when flash device is busy, 1 - busy flag is 0 when 238 * flash device is busy 239 */ 240 uint16_t busyBitPolarity; 241 /* [0x080-0x17f] Lookup table holds Flash command sequences */ 242 uint32_t lookupTable[64]; 243 /* [0x180-0x1af] Customizable LUT Sequences */ 244 flexspi_lut_seq_t lutCustomSeq[12]; 245 /* [0x1b0-0x1bf] Reserved for future use */ 246 uint32_t reserved4[4]; 247 } flexspi_mem_config_t; 248 249 /* 250 * Serial NOR configuration block 251 */ 252 typedef struct _flexspi_nor_config { 253 /* Common memory configuration info via FlexSPI */ 254 flexspi_mem_config_t memConfig; 255 /* Page size of Serial NOR */ 256 uint32_t pageSize; 257 /* Sector size of Serial NOR */ 258 uint32_t sectorSize; 259 /* Clock frequency for IP command */ 260 uint8_t ipcmdSerialClkFreq; 261 /* Sector/Block size is the same */ 262 uint8_t isUniformBlockSize; 263 /* The data order is swapped in OPI DDR mode */ 264 uint8_t isDataOrderSwapped; 265 /* Reserved for future use */ 266 uint8_t reserved0[5]; 267 /* Block size */ 268 uint32_t blockSize; 269 /* Flash State Context after being configured */ 270 uint32_t FlashStateCtx; 271 /* Reserved for future use */ 272 uint32_t reserve1[10]; 273 } flexspi_nor_config_t; 274 275 #endif /* __EVKMIMXRT1180_FLEXSPI_NOR_CONFIG__ */ 276