1 /* 2 * Copyright 2018-2019 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 * 7 */ 8 #ifndef __FLASH_CONFIG_H__ 9 #define __FLASH_CONFIG_H__ 10 #include <stdint.h> 11 #include "fsl_iap.h" 12 13 /*! @name Driver version */ 14 /*@{*/ 15 /*! @brief FLASH_CONFIG driver version 2.0.0. */ 16 #define FSL_FLASH_CONFIG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) 17 /*@}*/ 18 19 /* FLEXSPI memory config block related definitions */ 20 #define FLEXSPI_CFG_BLK_TAG (0x42464346UL) /* ascii "FCFB" Big Endian */ 21 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) /* V1.4.0 */ 22 23 /*! @brief FLEXSPI clock configuration - When clock source is PLL */ 24 enum { 25 kFlexSpiSerialClk_30MHz = 1, 26 kFlexSpiSerialClk_50MHz = 2, 27 kFlexSpiSerialClk_60MHz = 3, 28 kFlexSpiSerialClk_80MHz = 4, 29 kFlexSpiSerialClk_100MHz = 5, 30 kFlexSpiSerialClk_120MHz = 6, 31 kFlexSpiSerialClk_133MHz = 7, 32 kFlexSpiSerialClk_166MHz = 8, 33 kFlexSpiSerialClk_200MHz = 9, 34 }; 35 36 /*! @brief LUT instructions supported by FLEXSPI */ 37 #define CMD_SDR 0x01 38 #define CMD_DDR 0x21 39 #define RADDR_SDR 0x02 40 #define RADDR_DDR 0x22 41 #define CADDR_SDR 0x03 42 #define CADDR_DDR 0x23 43 #define MODE1_SDR 0x04 44 #define MODE1_DDR 0x24 45 #define MODE2_SDR 0x05 46 #define MODE2_DDR 0x25 47 #define MODE4_SDR 0x06 48 #define MODE4_DDR 0x26 49 #define MODE8_SDR 0x07 50 #define MODE8_DDR 0x27 51 #define WRITE_SDR 0x08 52 #define WRITE_DDR 0x28 53 #define READ_SDR 0x09 54 #define READ_DDR 0x29 55 #define LEARN_SDR 0x0A 56 #define LEARN_DDR 0x2A 57 #define DATSZ_SDR 0x0B 58 #define DATSZ_DDR 0x2B 59 #define DUMMY_SDR 0x0C 60 #define DUMMY_DDR 0x2C 61 #define DUMMY_RWDS_SDR 0x0D 62 #define DUMMY_RWDS_DDR 0x2D 63 #define JMP_ON_CS 0x1F 64 #define STOP_EXE 0 65 66 #define FLEXSPI_1PAD 0 67 #define FLEXSPI_2PAD 1 68 #define FLEXSPI_4PAD 2 69 #define FLEXSPI_8PAD 3 70 71 #define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ 72 (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | \ 73 FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ 74 FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) 75 76 /*! @brief FlexSPI Read Sample Clock Source definition */ 77 typedef enum _FlashReadSampleClkSource { 78 kFlexSPIReadSampleClk_LoopbackInternally = 0, 79 kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, 80 kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, 81 kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, 82 } flexspi_read_sample_clk_t; 83 84 /*! @brief Misc feature bit definitions */ 85 enum { 86 /* Bit for Differential clock enable */ 87 kFlexSpiMiscOffset_DiffClkEnable = 0, 88 /* Bit for Parallel mode enable */ 89 kFlexSpiMiscOffset_ParallelEnable = 2, 90 /* Bit for Word Addressable enable */ 91 kFlexSpiMiscOffset_WordAddressableEnable = 3, 92 /* Bit for Safe Configuration Frequency enable */ 93 kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, 94 /* Bit for Pad setting override enable */ 95 kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, 96 /* Bit for DDR clock confiuration indication. */ 97 kFlexSpiMiscOffset_DdrModeEnable = 6, 98 /* Bit for DLLCR settings under all modes */ 99 kFlexSpiMiscOffset_UseValidTimeForAllFreq = 7, 100 }; 101 102 #endif 103