1/*
2 * Copyright (c) 2024 S&C Electric Company <Michael.Banducci@sandc.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8#include <st/h7/stm32h755Xi_m7.dtsi>
9#include "nucleo_h755zi_q.dtsi"
10
11/*
12 * WARNING:
13 * Possible pin conflicts: The pins PA2 and PB13 may conflict on selection of
14 * ETH_STM32_HAL, since they are used in ST Zio or ST morpho connectors. To
15 * avoid conflicting states the jumpers JP6 and JP7 must be in ON state.
16 */
17
18/ {
19	model = "STMicroelectronics STM32H755ZI-Q-NUCLEO board";
20	compatible = "st,stm32h755zi-q-nucleo";
21
22	/* HW resources belonging to CM7 */
23	chosen {
24		zephyr,console = &usart3;
25		zephyr,shell-uart = &usart3;
26		zephyr,dtcm = &dtcm;
27		zephyr,sram = &sram0;
28		zephyr,flash = &flash0;
29		zephyr,canbus = &fdcan1;
30	};
31
32	pwmleds {
33		compatible = "pwm-leds";
34
35		red_pwm_led: red_pwm_led {
36			pwms = <&pwm12 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
37			label = "User LD3 - PWM12";
38		};
39	};
40
41	aliases {
42		led0 = &green_led;
43		pwm-led0 = &red_pwm_led;
44		sw0 = &user_button;
45	};
46};
47
48&clk_lsi {
49	status = "okay";
50};
51
52&clk_hsi48 {
53	status = "okay";
54};
55
56&clk_hse {
57	hse-bypass;
58	clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
59	status = "okay";
60};
61
62&pll {
63	div-m = <1>;
64	mul-n = <120>;
65	div-p = <2>;
66	div-q = <8>;
67	div-r = <2>;
68	clocks = <&clk_hse>;
69	status = "okay";
70};
71
72&pll2 {
73	div-m = <4>;
74	mul-n = <120>;
75	div-p = <2>;
76	div-q = <3>; /* gives 80MHz to the FDCAN */
77	div-r = <2>;
78	clocks = <&clk_hse>;
79	status = "okay";
80};
81
82&fdcan1 {
83	clocks = <&rcc STM32_CLOCK(APB1_2, 8)>,
84		 <&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>;
85	pinctrl-0 = <&fdcan1_rx_pd0 &fdcan1_tx_pd1>;
86	pinctrl-names = "default";
87	status = "okay";
88};
89
90&rcc {
91	clocks = <&pll>;
92	clock-frequency = <DT_FREQ_M(480)>;
93};
94
95&lpuart1 {
96	pinctrl-0 = <&lpuart1_tx_pb6 &lpuart1_rx_pb7>;
97	pinctrl-names = "default";
98	current-speed = <115200>;
99	status = "okay";
100};
101
102&usart3 {
103	pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>;
104	pinctrl-names = "default";
105	current-speed = <115200>;
106	status = "okay";
107};
108
109&rtc {
110	clocks = <&rcc STM32_CLOCK(APB4, 16)>,
111		 <&rcc STM32_SRC_LSI RTC_SEL(2)>;
112	status = "okay";
113};
114
115&i2c1 {
116	pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
117	pinctrl-names = "default";
118	status = "okay";
119	clock-frequency = <I2C_BITRATE_FAST>;
120};
121
122&timers12 {
123	st,prescaler = <10000>;
124	status = "okay";
125
126	pwm12: pwm {
127		status = "okay";
128		pinctrl-0 = <&tim12_ch1_pb14>;
129		pinctrl-names = "default";
130	};
131};
132
133&mac {
134	status = "okay";
135	pinctrl-0 = <&eth_ref_clk_pa1
136		     &eth_crs_dv_pa7
137		     &eth_rxd0_pc4
138		     &eth_rxd1_pc5
139		     &eth_tx_en_pg11
140		     &eth_txd0_pg13
141		     &eth_txd1_pb13>;
142	pinctrl-names = "default";
143	phy-connection-type = "rmii";
144	phy-handle = <&eth_phy>;
145};
146
147&mdio {
148	status = "okay";
149	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
150	pinctrl-names = "default";
151
152	eth_phy: ethernet-phy@0 {
153		compatible = "ethernet-phy";
154		reg = <0x00>;
155	};
156};
157
158&rng {
159	status = "okay";
160};
161
162zephyr_udc0: &usbotg_fs {
163	pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
164	pinctrl-names = "default";
165	status = "okay";
166};
167