1/*
2 * Copyright (c) 2022 Byte-Lab d.o.o. <dev@byte-lab.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8#include <st/h7/stm32h7b3Xi.dtsi>
9#include <st/h7/stm32h7b3lihxq-pinctrl.dtsi>
10#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
11#include "arduino_r3_connector.dtsi"
12#include <zephyr/dt-bindings/input/input-event-codes.h>
13
14/ {
15	model = "STMicroelectronics STM32H7B3I DISCOVERY KIT board";
16	compatible = "st,stm32h7b3i-dk";
17
18	chosen {
19		zephyr,console = &usart1;
20		zephyr,shell-uart = &usart1;
21		zephyr,sram = &sram0;
22		zephyr,flash = &flash0;
23		zephyr,display = &ltdc;
24		zephyr,canbus = &fdcan1;
25		zephyr,touch = &ft5336;
26	};
27
28	leds {
29		compatible = "gpio-leds";
30
31		red_led: led_0 {
32			gpios = <&gpiog 11 GPIO_ACTIVE_HIGH>;
33			label = "User LD1";
34		};
35
36		blue_led: led_1 {
37			gpios = <&gpiog 2 GPIO_ACTIVE_HIGH>;
38			label = "User LD2";
39		};
40	};
41
42	gpio_keys {
43		compatible = "gpio-keys";
44
45		user_button: button {
46			label = "User PB";
47			gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
48			zephyr,code = <INPUT_KEY_0>;
49		};
50	};
51
52	lvgl_pointer {
53		compatible = "zephyr,lvgl-pointer-input";
54		input = <&ft5336>;
55	};
56
57	sdram2: sdram@d0000000 {
58		compatible = "zephyr,memory-region", "mmio-sram";
59		device_type = "memory";
60		reg = <0xd0000000 DT_SIZE_M(16)>;
61		zephyr,memory-region = "SDRAM2";
62		/* Frame buffer memory cache will cause screen flickering. */
63		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
64	};
65
66	octo_nor: memory@90000000 {
67		compatible = "zephyr,memory-region";
68		reg = <0x90000000 DT_SIZE_M(64)>;
69		zephyr,memory-region = "EXTMEM";
70		/* The ATTR_MPU_EXTMEM attribut causing a MPU FAULT */
71		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>;
72	};
73
74	transceiver0: can-phy0 {
75		compatible = "microchip,mcp2562fd", "can-transceiver-gpio";
76		standby-gpios = <&gpioh 8 GPIO_ACTIVE_HIGH>;
77		max-bitrate = <5000000>;
78		#phy-cells = <0>;
79	};
80
81	dcmi_camera_connector: connector_dcmi_camera {
82		compatible = "st,stm32-dcmi-camera-fpu-330zh";
83		#gpio-cells = <2>;
84		gpio-map-mask = <0xffffffff 0xffffffc0>;
85		gpio-map-pass-thru = <0 0x3f>;
86		gpio-map = <3  0 &gpiod 12  0>,  /* I2C4_SCL */
87			   <4  0 &gpiod 13  0>,  /* I2C4_SDA */
88			   <5  0 &gpioa  0  0>,  /* RESET# */
89			   <6  0 &gpioa  7  0>,  /* PWDN_EN */
90			   <12 0 &gpiob  7  0>,  /* DCMI_VSYNC */
91			   <14 0 &gpioa  4  0>,  /* DCMI_HSYNC */
92			   <16 0 &gpioa  6  0>,  /* DCMI_PIXCK */
93			   <20 0 &gpiob  9  0>,  /* DCMI_D7 */
94			   <21 0 &gpiob  8  0>,  /* DCMI_D6 */
95			   <22 0 &gpiod  3  0>,  /* DCMI_D5 */
96			   <23 0 &gpioc 11  0>,  /* DCMI_D4 */
97			   <24 0 &gpioc  9  0>,  /* DCMI_D3 */
98			   <25 0 &gpiog 10  0>,  /* DCMI_D2 */
99			   <26 0 &gpioc  7  0>,  /* DCMI_D1 */
100			   <27 0 &gpioc  6  0>;  /* DCMI_D0 */
101	};
102
103	aliases {
104		led0 = &blue_led;
105		led1 = &red_led;
106		sw0 = &user_button;
107	};
108};
109
110&clk_hsi48 {
111	status = "okay";
112};
113
114&clk_hse {
115	clock-frequency = <DT_FREQ_M(24)>;
116	status = "okay";
117};
118
119/* PLL1P is used for system clock (280 MHz), PLL1Q is used for FDCAN bit quantum clock (80 MHz) */
120&pll {
121	div-m = <12>;
122	mul-n = <280>;
123	div-p = <2>;
124	div-q = <7>;
125	div-r = <2>;
126	clocks = <&clk_hse>;
127	status = "okay";
128};
129
130/* PLL3R is used for outputting 9 MHz pixel clock for LTDC */
131&pll3 {
132	div-m = <8>;
133	mul-n = <60>;
134	div-p = <2>;
135	div-q = <2>;
136	div-r = <20>;
137	clocks = <&clk_hse>;
138	status = "okay";
139};
140
141&rcc {
142	clocks = <&pll>;
143	clock-frequency = <DT_FREQ_M(280)>;
144	d1cpre = <1>;
145	hpre = <1>;
146	d1ppre = <2>;
147	d2ppre1 = <2>;
148	d2ppre2 = <2>;
149	d3ppre = <2>;
150};
151
152&usart1 {
153	pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
154	pinctrl-names = "default";
155	current-speed = <115200>;
156	status = "okay";
157};
158
159&uart4 {
160	pinctrl-0 = <&uart4_tx_ph13 &uart4_rx_ph14>;
161	pinctrl-names = "default";
162	current-speed = <115200>;
163	status = "okay";
164};
165
166&i2c4 {
167	pinctrl-0 = <&i2c4_scl_pd12 &i2c4_sda_pd13>;
168	pinctrl-names = "default";
169	clock-frequency = <I2C_BITRATE_FAST>;
170	status = "okay";
171
172	ft5336: ft5336@38 {
173		compatible = "focaltech,ft5336";
174		reg = <0x38>;
175		int-gpios = <&gpioh 2 GPIO_ACTIVE_LOW>;
176	};
177};
178
179&spi2 {
180	pinctrl-0 = <&spi2_sck_pa12 &spi2_miso_pb14 &spi2_mosi_pb15 &spi2_nss_pi0>;
181	pinctrl-names = "default";
182	status = "okay";
183};
184
185/* Connect solder bridges SB3, SB4 and SB5 to use CAN connector (CN21) */
186&fdcan1 {
187	pinctrl-0 = <&fdcan1_rx_pa11 &fdcan1_tx_pa12>;
188	pinctrl-names = "default";
189	clocks = <&rcc STM32_CLOCK(APB1_2, 8)>,
190		 <&rcc STM32_SRC_PLL1_Q FDCAN_SEL(1)>;
191	phys = <&transceiver0>;
192	status = "okay";
193};
194
195&fmc {
196	pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1
197		     &fmc_sdclk_pg8 &fmc_sdnwe_ph5 &fmc_sdcke1_ph7
198		     &fmc_sdne1_ph6 &fmc_sdnras_pf11 &fmc_sdncas_pg15
199		     &fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4
200		     &fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14
201		     &fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1
202		     &fmc_a14_pg4 &fmc_a15_pg5 &fmc_d0_pd14 &fmc_d1_pd15
203		     &fmc_d2_pd0 &fmc_d3_pd1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9
204		     &fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13
205		     &fmc_d11_pe14 &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9
206		     &fmc_d15_pd10>;
207	pinctrl-names = "default";
208	status = "okay";
209
210	sdram {
211		status = "okay";
212		power-up-delay = <100>;
213		num-auto-refresh = <8>;
214		mode-register = <0x220>;
215		refresh-rate = <0x603>;
216
217		bank@1 {
218			reg = <1>;
219			st,sdram-control = <STM32_FMC_SDRAM_NC_9
220						STM32_FMC_SDRAM_NR_12
221						STM32_FMC_SDRAM_MWID_16
222						STM32_FMC_SDRAM_NB_4
223						STM32_FMC_SDRAM_CAS_2
224						STM32_FMC_SDRAM_SDCLK_PERIOD_3
225						STM32_FMC_SDRAM_RBURST_ENABLE
226						STM32_FMC_SDRAM_RPIPE_2>;
227			st,sdram-timing = <2 7 4 7 2 2 2>;
228		};
229	};
230};
231
232&sdmmc1 {
233	pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9
234		     &sdmmc1_d2_pc10 &sdmmc1_d3_pc11
235		     &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>;
236	pinctrl-names = "default";
237	cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
238	disk-name = "SD";
239	status = "okay";
240};
241
242&ltdc {
243	pinctrl-0 = <&ltdc_r0_pi15 &ltdc_r1_pj0 &ltdc_r2_pj1 &ltdc_r3_pj2
244		     &ltdc_r4_pj3 &ltdc_r5_pj4 &ltdc_r6_pj5 &ltdc_r7_pj6
245		     &ltdc_g0_pj7 &ltdc_g1_pj8 &ltdc_g2_pj9 &ltdc_g3_pj10
246		     &ltdc_g4_pj11 &ltdc_g5_pk0 &ltdc_g6_pk1 &ltdc_g7_pk2
247		     &ltdc_b0_pj12 &ltdc_b1_pj13 &ltdc_b2_pj14 &ltdc_b3_pj15
248		     &ltdc_b4_pk3 &ltdc_b5_pk4 &ltdc_b6_pk5 &ltdc_b7_pk6
249		     &ltdc_de_pk7 &ltdc_clk_pi14 &ltdc_hsync_pi12 &ltdc_vsync_pi13>;
250	pinctrl-names = "default";
251	disp-on-gpios = <&gpioa 2 GPIO_ACTIVE_HIGH>;
252	bl-ctrl-gpios = <&gpioa 1 GPIO_ACTIVE_HIGH>;
253	ext-sdram = <&sdram2>;
254	status = "okay";
255
256	width = <480>;
257	height = <272>;
258	pixel-format = <PANEL_PIXEL_FORMAT_RGB_565>;
259
260	display-timings {
261		compatible = "zephyr,panel-timing";
262		de-active = <0>;
263		pixelclk-active = <0>;
264		hsync-active = <0>;
265		vsync-active = <0>;
266		hsync-len = <1>;
267		vsync-len = <10>;
268		hback-porch = <43>;
269		vback-porch = <12>;
270		hfront-porch = <8>;
271		vfront-porch = <4>;
272	};
273
274	def-back-color-red = <0xFF>;
275	def-back-color-green = <0xFF>;
276	def-back-color-blue = <0xFF>;
277};
278
279&octospi1 {
280	pinctrl-0 = <&octospim_p1_clk_pb2 &octospim_p1_ncs_pg6
281		     &octospim_p1_io0_pd11 &octospim_p1_io1_pf9
282		     &octospim_p1_io2_pf7 &octospim_p1_io3_pf6
283		     &octospim_p1_io4_pc1 &octospim_p1_io5_ph3
284		     &octospim_p1_io6_pg9 &octospim_p1_io7_pd7
285		     &octospim_p1_dqs_pc5>;
286	pinctrl-names = "default";
287
288	status = "okay";
289
290	mx25lm51245: ospi-nor-flash@0 {
291		compatible = "st,stm32-ospi-nor";
292		reg = <0>;
293		size = <DT_SIZE_M(512)>; /* 512 Megabits */
294		ospi-max-frequency = <DT_FREQ_M(50)>;
295		spi-bus-width = <OSPI_OPI_MODE>;
296		data-rate = <OSPI_DTR_TRANSFER>;
297		status = "okay";
298
299		partitions {
300			compatible = "fixed-partitions";
301			#address-cells = <1>;
302			#size-cells = <1>;
303
304			partition@0 {
305				label = "nor";
306				reg = <0x00000000 DT_SIZE_M(4)>;
307			};
308		};
309	};
310};
311
312st_cam_i2c: &i2c4 {};
313
314st_cam_dvp: &dcmi {};
315