1.. zephyr:board:: stm32mp257f_ev1
2
3Overview
4********
5
6The STM32MP257F-EV1 Evaluation board is designed as a complete demonstration
7and development platform for the STMicroelectronics STM32MP257F microprocessor
8based on Arm |reg| dual-core Cortex |reg|-A35 (1.5 GHz) and Cortex |reg|-M33
9(400 MHz), and the STPMIC25APQR companion chip.
10Zephyr OS is ported to run on the Cortex |reg|-M33 core, as a coprocessor of
11the Cortex |reg|-A35 core.
12
13Features:
14=========
15
16- STM32MP257FAI3 microprocessor featuring dual-core Arm |reg| Cortex |reg|-A35,
17  a Cortex |reg|-M33 and a Cortex |reg|-M0+ in a TFBGA436 package
18- ST power management STPMIC25APQR
19- Two 16-Gbit DDR4 DRAMs
20- 512-Mbit (64 Mbytes) S-NOR flash memory
21- 32-Gbit (4 Gbytes) eMMC v5.0
22- Three 1-Gbit/s Ethernet (RGMII) with TSN switch compliant with IEEE-802.3ab
23- High-speed USB Host 2-port hub
24- High-speed USB Type-C |reg| DRP
25- Four user LEDs
26- Two user, one tamper, and one reset push-buttons
27- One wake-up button
28- Four boot pin switches
29- Board connectors:
30
31  - Three Ethernet RJ45
32  - Two USB Host Type-A
33  - USB Type-C |reg|
34  - microSD |trade| card holder
35  - Mini PCIe
36  - Dual-lane MIPI CSI-2 |reg| camera module expansion connector
37  - Two CAN FD
38  - LVDS
39  - MIPI10
40  - GPIO expansion connector
41  - mikroBUS |trade| expansion connector
42  - VBAT for power backup
43
44- On-board STLINK-V3EC debugger/programmer with USB re-enumeration capability
45  Two Virtual COM ports (VCPs), and debug ports (JTAG/SWD)
46- Mainlined open-source Linux |reg| STM32 MPU OpenSTLinux Distribution and
47  STM32CubeMP2 software with examples
48- Linux |reg| Yocto project, Buildroot, and STM32CubeIDE as
49  development environments
50
51More information about the board can be found at the
52`STM32MP257F-EV1 website`_.
53
54Hardware
55********
56
57Cores:
58======
59
60- 64-bit dual-core Arm |reg| Cortex |reg|-A35 with 1.5 GHz max frequency
61  - 32-Kbyte I + 32-Kbyte D level 1 cache for each Cortex |reg|-A35 core
62  - 512-Kbyte unified level 2 cache
63  - Arm |reg| NEON |trade| and Arm |reg| TrustZone |reg|
64- 32-bit Arm |reg| Cortex |reg|-M33 with FPU/MPU, Arm |reg| TrustZone |reg|,
65  and 400 MHz max frequency
66  - L1 16-Kbyte ICache / 16-Kbyte DCache for Cortex |reg|-M33
67- 32-bit Arm |reg| Cortex |reg|-M0+ in SmartRun domain with 200 MHz max
68  frequency (up to 16 MHz in autonomous mode)
69
70Memories:
71=========
72
73- External DDR memory up to 4 Gbytes
74  - Up to DDR3L-2133 16/32-bit
75  - Up to DDR4-2400 16/32-bit
76  - Up to LPDDR4-2400 16/32-bit
77- 808-Kbyte internal SRAM: 256-Kbyte AXI SYSRAM, 128-Kbyte AXI video RAM or
78  SYSRAM extension, 256-Kbyte AHB SRAM, 128-Kbyte AHB SRAM with ECC in backup
79  domain, 8-Kbyte SRAM with ECC in backup domain, 32 Kbytes in SmartRun domain
80- Two Octo-SPI memory interfaces
81- Flexible external memory controller with up to 16-bit data bus: parallel
82  interface to connect external ICs, and SLC NAND memories with up to 8-bit ECC
83
84Power
85=====
86
87- STPMIC25 for voltage regulation (multiple buck/LDO regulators)
88- USB-C or 5V DC jack power input
89- VBAT backup battery connector (RTC, backup SRAM)
90
91Clock management
92================
93
94- External oscillators:
95  - 32.768 kHz LSE crystal
96  - 40 MHz HSE crystal
97- Internal oscillators:
98  - 64 MHz HSI oscillator
99  - 4 MHz CSI oscillator
100  - 32 kHz LSI oscillator
101  - Five separate PLLs with integer and fractional mode
102
103Security/Safety
104===============
105
106- Secure boot, TrustZone |reg| peripherals, active tamper, environmental
107  monitors, display secure layers, hardware accelerators
108- Complete resource isolation framework
109
110Connectivity
111============
112
113- 3x Gigabit Ethernet (RGMII, TSN switch capable)
114- 2x CAN FD
115- USB 2.0 High-Speed Host (dual-port)
116- USB Type-C |reg| DRP
117- mikroBUS |trade| expansion
118- GPIO expansion connector
119
120Display & Camera
121================
122
123- DSI interface (4-lane)
124- LVDS interface (4-lane)
125- Camera CSI-2 interface (2-lane)
126
127Debug
128=====
129
130- STLINK-V3EC (onboard debugger with VCP, JTAG and SWD)
131
132More information about STM32MP257F can be found here:
133
134- `STM32MP257F on www.st.com`_
135
136Supported Features
137==================
138
139.. zephyr:board-supported-hw::
140
141Connections and IOs
142===================
143
144STM32MP257F-EV1 Evaluation Board schematic is available here:
145`STM32MP257F-EV1 Evaluation board schematics`_
146
147System Clock
148============
149
150Cortex |reg|-A35
151----------------
152
153Not yet supported in Zephyr.
154
155Cortex |reg|-M33
156----------------
157
158The Cortex |reg|-M33 Core is configured to run at a 400 MHz clock speed.
159
160Programming and Debugging
161*************************
162
163.. zephyr:board-supported-runners::
164
165Prerequisite
166============
167
168Before you can run Zephyr on the STM32MP257F-EV1 Evaluation board, you need to
169set up the Cortex |reg|-A35 core with a Linux |reg| environment. The Cortex
170|reg|-M33 core runs Zephyr as a coprocessor, and it requires the Cortex
171|reg|-A35 to load and start the firmware using remoteproc.
172
173One way to set up the Linux environment is to use the official ST
174OpenSTLinux distribution, following the `Starter Package`_. (more information
175about the procedure can be found in the `STM32MPU Wiki`_)
176
177Loading the firmware
178====================
179
180Once the OpenSTLinux distribution is installed on the board, the Cortex |reg|
181-A35 is responsible (in the current distribution) for loading the Zephyr
182firmware image in DDR and/or SRAM and starting the Cortex |reg| -M33 core. The
183application can be built using west, taking the :zephyr:code-sample:`blinky` as
184an example.
185
186.. zephyr-app-commands::
187   :zephyr-app: samples/basic/blinky
188   :board: stm32mp257f_ev1/stm32mp257fxx/m33
189   :goals: build
190
191The firmware can be copied to the board file system and started with the Linux
192remoteproc framework. (more information about the procedure can be found in the
193`STM32MP257F boot Cortex-M33 firmware`_)
194
195Debugging
196=========
197Applications can be debugged using OpenOCD and GDB. The OpenOCD files can be
198found at `device-stm-openocd`_.
199The firmware must first be started by the Cortex |reg|-A35. The debugger can
200then be attached to the running Zephyr firmware using OpenOCD.
201
202- Build the sample:
203
204.. zephyr-app-commands::
205   :zephyr-app: samples/basic/blinky
206   :board: stm32mp257f_ev1/stm32mp257fxx/m33
207   :goals: build
208
209- Copy the firmware to the board, load it and start it with remoteproc
210  (`STM32MP257F boot Cortex-M33 firmware`_). The orange LED should be blinking.
211- Attach to the target:
212
213.. code-block:: console
214
215   $ west attach
216
217References
218==========
219
220.. target-notes::
221
222.. _STM32MP257F-EV1 website:
223  https://www.st.com/en/evaluation-tools/stm32mp257f-ev1.html#overview
224
225.. _STM32MP257F-EV1 Evaluation board User Manual:
226  https://www.st.com/resource/en/user_manual/um3359-evaluation-board-with-stm32mp257f-mpu-stmicroelectronics.pdf
227
228.. _STM32MP257F-EV1 Evaluation board schematics:
229  https://www.st.com/resource/en/schematic_pack/mb1936-mp257f-x-d01-schematic.pdf
230
231.. _STM32MP25xC/F Evaluation board datasheet:
232  https://www.st.com/resource/en/datasheet/stm32mp257c.pdf
233
234.. _STM32MP257F on www.st.com:
235  https://www.st.com/en/microcontrollers-microprocessors/stm32mp257f.html
236
237.. _STM32MP257F reference manual:
238  https://www.st.com/resource/en/reference_manual/rm0457-stm32mp25xx-advanced-armbased-3264bit-mpus-stmicroelectronics.pdf
239
240.. _STM32MP257F boot Cortex-M33 firmware:
241  https://wiki.st.com/stm32mpu/wiki/Linux_remoteproc_framework_overview#Remote_processor_boot_through_sysfs
242
243.. _Starter Package:
244  https://wiki.st.com/stm32mpu/wiki/STM32MP25_Evaluation_boards_-_Starter_Package
245
246.. _STM32MPU Wiki:
247  https://wiki.st.com/stm32mpu/wiki/Main_Page
248
249.. _device-stm-openocd:
250  https://github.com/STMicroelectronics/device-stm-openocd/tree/main
251