1/*
2 * Copyright (c) 2025 STMicroelectronics
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8#include <st/u5/stm32u5g9Xj.dtsi>
9#include <st/u5/stm32u5g9zjtxq-pinctrl.dtsi>
10#include <zephyr/dt-bindings/display/panel.h>
11#include <zephyr/dt-bindings/input/input-event-codes.h>
12
13/ {
14	model = "STMicroelectronics STM32U5G9J DISCOVERY-2 KIT board";
15	compatible = "st,stm32u5g9j-dk2";
16
17	chosen {
18		zephyr,console = &usart1;
19		zephyr,shell-uart = &usart1;
20		zephyr,sram = &sram0;
21		zephyr,flash = &flash0;
22		zephyr,code-partition = &slot0_partition;
23		zephyr,display = &ltdc;
24		zephyr,touch = &gt911;
25	};
26
27	leds {
28		compatible = "gpio-leds";
29
30		green_led_0: led_3 {
31			gpios = <&gpiod 4 GPIO_ACTIVE_HIGH>;
32			label = "User LD3";
33		};
34
35		red_led_0: led_2 {
36			gpios = <&gpiod 2 GPIO_ACTIVE_HIGH>;
37			label = "User LD2";
38		};
39	};
40
41	gpio_keys {
42		compatible = "gpio-keys";
43
44		user_button: button_0 {
45			label = "User";
46			gpios = <&gpioc 13 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
47			zephyr,code = <INPUT_KEY_0>;
48		};
49	};
50
51	aliases {
52		led0 = &green_led_0;
53		led1 = &red_led_0;
54		sw0 = &user_button;
55		sdhc0 = &sdmmc1; /* disabled by default : conflict with ltdc node */
56		watchdog0 = &iwdg;
57		die-temp0 = &die_temp;
58		volt-sensor0 = &vref1;
59		volt-sensor1 = &vbat4;
60	};
61
62	ext_memory: memory@a0000000 {
63		compatible = "zephyr,memory-region";
64		reg = <0xa0000000 DT_SIZE_M(128)>;
65		zephyr,memory-region = "EXTMEM";
66		/* The ATTR_MPU_EXTMEM attribut causing a MPU FAULT */
67		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>;
68	};
69};
70
71&ltdc {
72	pinctrl-0 = <&ltdc_r0_pc6 &ltdc_r1_pc7 &ltdc_r2_pe15 &ltdc_r3_pd8
73			&ltdc_r4_pd9 &ltdc_r5_pd10 &ltdc_r6_pd11 &ltdc_r7_pd12
74			&ltdc_g0_pc8 &ltdc_g1_pc9 &ltdc_g2_pe9 &ltdc_g3_pe10
75			&ltdc_g4_pe11 &ltdc_g5_pe12 &ltdc_g6_pe13 &ltdc_g7_pe14
76			&ltdc_b0_pb9 &ltdc_b1_pb2 &ltdc_b2_pd14 &ltdc_b3_pd15
77			&ltdc_b4_pd0 &ltdc_b5_pd1 &ltdc_b6_pe7 &ltdc_b7_pe8
78			&ltdc_de_pd6 &ltdc_clk_pd3 &ltdc_hsync_pe0 &ltdc_vsync_pd13>;
79	pinctrl-names = "default";
80	disp-on-gpios = <&gpioe 4 GPIO_ACTIVE_HIGH>;
81	bl-ctrl-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>;
82	status = "okay";
83
84	width = <800>;
85	height = <480>;
86	pixel-format = <PANEL_PIXEL_FORMAT_RGB_888>;
87
88	def-back-color-red = <0x00>;
89	def-back-color-green = <0x00>;
90	def-back-color-blue = <0x00>;
91
92	display-timings {
93		compatible = "zephyr,panel-timing";
94		de-active = <0>;
95		pixelclk-active = <0>;
96		hsync-active = <0>;
97		vsync-active = <0>;
98		hsync-len = <5>;
99		vsync-len = <5>;
100		hback-porch = <8>;
101		vback-porch = <8>;
102		hfront-porch = <8>;
103		vfront-porch = <14>;
104	};
105};
106
107&clk_hsi48 {
108	status = "okay";
109};
110
111&clk_hse {
112	clock-frequency = <DT_FREQ_M(16)>;
113	status = "okay";
114};
115
116&clk_msis {
117	status = "okay";
118	msi-range = <4>; /* 4MHz (reset value) */
119	msi-pll-mode;
120};
121
122&clk_lse {
123	status = "okay";
124};
125
126&pll1 {
127	div-m = <4>;
128	mul-n = <80>;
129	div-p = <2>;
130	div-q = <2>;
131	div-r = <2>;
132	clocks = <&clk_hse>;
133	status = "okay";
134};
135
136&pll2 {
137	div-m = <4>;
138	mul-n = <66>;
139	div-p = <2>;
140	div-q = <2>;
141	div-r = <2>;
142	clocks = <&clk_hse>;
143	status = "okay";
144};
145
146&pll3 {
147	div-m = <4>;
148	mul-n = <125>;
149	div-p = <20>;
150	div-q = <20>;
151	div-r = <20>;
152	clocks = <&clk_hse>;
153	status = "okay";
154};
155
156&rcc {
157	clocks = <&pll1>;
158	clock-frequency = <DT_FREQ_M(160)>;
159	ahb-prescaler = <1>;
160	apb1-prescaler = <1>;
161	apb2-prescaler = <1>;
162	apb3-prescaler = <1>;
163};
164
165&usart1 {
166	pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
167	pinctrl-names = "default";
168	current-speed = <115200>;
169	status = "okay";
170};
171
172&usart2 {
173	pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>;
174	pinctrl-names = "default";
175	current-speed = <115200>;
176	status = "okay";
177};
178
179&i2c1 {
180	pinctrl-0 = <&i2c1_scl_pg14 &i2c1_sda_pg13>;
181	pinctrl-names = "default";
182	status = "okay";
183	clock-frequency = <I2C_BITRATE_STANDARD>;
184};
185
186&i2c2 {
187	pinctrl-names = "default";
188	pinctrl-0 = <&i2c2_scl_pf1 &i2c2_sda_pf0>;
189	status = "okay";
190	clock-frequency = <I2C_BITRATE_FAST>;
191
192	gt911: gt911@5d {
193		compatible = "goodix,gt911";
194		reg = <0x5d>;
195		irq-gpios = <&gpioe 5 GPIO_ACTIVE_HIGH>;
196		reset-gpios = <&gpiod 2 GPIO_ACTIVE_LOW>;
197	};
198};
199
200&spi1 {
201	pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pb5>;
202	pinctrl-names = "default";
203	cs-gpios = <&gpiob 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
204	status = "okay";
205};
206
207&timers1 {
208	st,prescaler = <1>;
209	status = "okay";
210
211	pwm1: pwm {
212		status = "okay";
213		pinctrl-0 = <&tim1_ch2_pe11>;
214		pinctrl-names = "default";
215	};
216};
217
218&timers2 {
219	st,prescaler = <1>;
220	status = "okay";
221
222	pwm2: pwm {
223		status = "okay";
224		pinctrl-0 = <&tim2_ch4_pa3>;
225		pinctrl-names = "default";
226	};
227};
228
229/* Connected to onboard 4-Gbyte eMMC flash memory */
230&sdmmc1 {
231	pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9
232		&sdmmc1_d2_pc10 &sdmmc1_d3_pc11
233		&sdmmc1_d4_pb8 &sdmmc1_d5_pb9
234		&sdmmc1_d6_pc6 &sdmmc1_d7_pc7
235		&sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>;
236	pinctrl-names = "default";
237	/* disabled due to conflicting pins pc6, pc7, pc8
238	 * pc9 and pb9 with LTDC node.
239	 */
240	status = "disabled";
241};
242
243&gpdma1 {
244	status = "okay";
245};
246
247&adc1 {
248	pinctrl-0 = <&adc1_in5_pa0 &adc1_in12_pa7>;
249	pinctrl-names = "default";
250	st,adc-clock-source = "ASYNC";
251	st,adc-prescaler = <1>;
252	status = "okay";
253
254	#address-cells = <1>;
255	#size-cells = <0>;
256
257	channel@5 {
258		reg = <0x5>;
259		zephyr,gain = "ADC_GAIN_1";
260		zephyr,reference = "ADC_REF_INTERNAL";
261		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
262		zephyr,resolution = <14>;
263	};
264
265	channel@c {
266		reg = <0xc>;
267		zephyr,gain = "ADC_GAIN_1";
268		zephyr,reference = "ADC_REF_INTERNAL";
269		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
270		zephyr,resolution = <14>;
271	};
272};
273
274&adc4 {
275	pinctrl-0 = <&adc4_in4_pc3>;
276	pinctrl-names = "default";
277	st,adc-clock-source = "ASYNC";
278	st,adc-prescaler = <1>;
279	status = "okay";
280
281	#address-cells = <1>;
282	#size-cells = <0>;
283
284	channel@4 {
285		reg = <0x4>;
286		zephyr,gain = "ADC_GAIN_1";
287		zephyr,reference = "ADC_REF_INTERNAL";
288		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
289		zephyr,resolution = <12>;
290	};
291};
292
293zephyr_udc0: &usbotg_hs {
294	pinctrl-0 = <&usb_otg_hs_dm_pa11 &usb_otg_hs_dp_pa12>;
295	pinctrl-names = "default";
296	status = "okay";
297};
298
299&otghs_phy {
300	clock-reference = "SYSCFG_OTG_HS_PHY_CLK_16MHz";
301};
302
303&flash0 {
304	partitions {
305		compatible = "fixed-partitions";
306		#address-cells = <1>;
307		#size-cells = <1>;
308
309		/*
310		 * Following flash partition is dedicated to the use of bootloader
311		 */
312		boot_partition: partition@0 {
313			label = "mcuboot";
314			reg = <0x00000000 DT_SIZE_K(64)>;
315		};
316
317		slot0_partition: partition@10000 {
318			label = "image-0";
319			reg = <0x00010000 DT_SIZE_K(1952)>;
320		};
321
322		slot1_partition: partition@1f8000 {
323			label = "image-1";
324			reg = <0x001f8000 DT_SIZE_K(1960)>;
325		};
326
327		storage_partition: partition@3e2000 {
328			label = "storage";
329			reg = <0x003e2000 DT_SIZE_K(120)>;
330		};
331	};
332};
333
334&xspi1 {
335	clocks = <&rcc STM32_CLOCK(AHB2_2, 12U)>,
336			 <&rcc STM32_SRC_PLL2_Q HSPI_SEL(2)>;
337
338	pinctrl-0 = <&hspi1_dqs0_pi2 &hspi1_ncs_ph9
339		&hspi1_io0_ph10 &hspi1_io1_ph11
340		&hspi1_io2_ph12 &hspi1_io3_ph13
341		&hspi1_io4_ph14 &hspi1_io5_ph15
342		&hspi1_io6_pi0 &hspi1_io7_pi1
343		&hspi1_clk_pi3>;
344	pinctrl-names = "default";
345	status = "okay";
346
347	mx66lm1g45: xspi-nor-flash@0 {
348		compatible = "st,stm32-xspi-nor";
349		reg = <0>;
350		size = <DT_SIZE_M(1024)>; /* 1 Gbits */
351		ospi-max-frequency = <DT_FREQ_M(133)>;
352		spi-bus-width = <XSPI_OCTO_MODE>;
353		data-rate = <XSPI_DTR_TRANSFER>;
354		four-byte-opcodes;
355		status = "okay";
356
357		partitions {
358			compatible = "fixed-partitions";
359			#address-cells = <1>;
360			#size-cells = <1>;
361
362			extflash_partition: partition@0 {
363				label = "ext_storage";
364				reg = <0 DT_SIZE_M(128)>;
365			};
366		};
367	};
368};
369
370&rtc {
371	clocks =  <&rcc STM32_CLOCK(APB3, 21)>,
372			  <&rcc STM32_SRC_LSE RTC_SEL(1)>;
373	status = "okay";
374};
375
376&iwdg {
377	status = "okay";
378};
379
380&rng {
381	status = "okay";
382};
383
384&die_temp {
385	status = "okay";
386};
387
388&vref1 {
389	status = "okay";
390};
391
392&vbat4 {
393	status = "okay";
394};
395