1 /* 2 * Copyright (c) 2018 Intel Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef __INC_BOARD_H 8 #define __INC_BOARD_H 9 10 /* Map APL GPIO pins to pins on UP Squared HAT */ 11 #define UP2_HAT_PIN_3_DEV APL_GPIO_DEV_N_0 12 #define UP2_HAT_PIN_3 APL_GPIO_28 13 14 #define UP2_HAT_PIN_5_DEV APL_GPIO_DEV_N_0 15 #define UP2_HAT_PIN_5 APL_GPIO_29 16 17 #define UP2_HAT_PIN_7_DEV APL_GPIO_DEV_NW_2 18 #define UP2_HAT_PIN_7 APL_GPIO_123 19 20 #define UP2_HAT_PIN_8_DEV APL_GPIO_DEV_N_1 21 #define UP2_HAT_PIN_8 APL_GPIO_43 22 23 #define UP2_HAT_PIN_10_DEV APL_GPIO_DEV_N_1 24 #define UP2_HAT_PIN_10 APL_GPIO_42 25 26 #define UP2_HAT_PIN_11_DEV APL_GPIO_DEV_N_1 27 #define UP2_HAT_PIN_11 APL_GPIO_44 28 29 #define UP2_HAT_PIN_12_DEV APL_GPIO_DEV_W_0 30 #define UP2_HAT_PIN_12 APL_GPIO_146 31 32 #define UP2_HAT_PIN_13_DEV APL_GPIO_DEV_NW_2 33 #define UP2_HAT_PIN_13 APL_GPIO_122 34 35 #define UP2_HAT_PIN_15_DEV APL_GPIO_DEV_NW_2 36 #define UP2_HAT_PIN_15 APL_GPIO_121 37 38 #define UP2_HAT_PIN_16_DEV APL_GPIO_DEV_N_1 39 #define UP2_HAT_PIN_16 APL_GPIO_37 40 41 #define UP2_HAT_PIN_18_DEV APL_GPIO_DEV_NW_1 42 #define UP2_HAT_PIN_18 APL_GPIO_88 43 44 #define UP2_HAT_PIN_19_DEV APL_GPIO_DEV_NW_2 45 #define UP2_HAT_PIN_19 APL_GPIO_110 46 47 #define UP2_HAT_PIN_21_DEV APL_GPIO_DEV_NW_2 48 #define UP2_HAT_PIN_21 APL_GPIO_109 49 50 #define UP2_HAT_PIN_22_DEV APL_GPIO_DEV_NW_1 51 #define UP2_HAT_PIN_22 APL_GPIO_85 52 53 #define UP2_HAT_PIN_23_DEV APL_GPIO_DEV_NW_1 54 #define UP2_HAT_PIN_23 APL_GPIO_104 55 56 #define UP2_HAT_PIN_24_DEV APL_GPIO_DEV_NW_1 57 #define UP2_HAT_PIN_24 APL_GPIO_105 58 59 #define UP2_HAT_PIN_26_DEV APL_GPIO_DEV_NW_1 60 #define UP2_HAT_PIN_26 APL_GPIO_106 61 62 #define UP2_HAT_PIN_27_DEV APL_GPIO_DEV_N_0 63 #define UP2_HAT_PIN_27 APL_GPIO_30 64 65 #define UP2_HAT_PIN_28_DEV APL_GPIO_DEV_N_0 66 #define UP2_HAT_PIN_28 APL_GPIO_31 67 68 #define UP2_HAT_PIN_29_DEV APL_GPIO_DEV_NW_2 69 #define UP2_HAT_PIN_29 APL_GPIO_120 70 71 #define UP2_HAT_PIN_31_DEV APL_GPIO_DEV_NW_1 72 #define UP2_HAT_PIN_31 APL_GPIO_87 73 74 #define UP2_HAT_PIN_32_DEV APL_GPIO_DEV_N_1 75 #define UP2_HAT_PIN_32 APL_GPIO_34 76 77 #define UP2_HAT_PIN_33_DEV APL_GPIO_DEV_N_1 78 #define UP2_HAT_PIN_33 APL_GPIO_35 79 80 #define UP2_HAT_PIN_35_DEV APL_GPIO_DEV_W_0 81 #define UP2_HAT_PIN_35 APL_GPIO_147 82 83 #define UP2_HAT_PIN_36_DEV APL_GPIO_DEV_N_1 84 #define UP2_HAT_PIN_36 APL_GPIO_45 85 86 #define UP2_HAT_PIN_37_DEV APL_GPIO_DEV_NW_1 87 #define UP2_HAT_PIN_37 APL_GPIO_86 88 89 #define UP2_HAT_PIN_38_DEV APL_GPIO_DEV_W_0 90 #define UP2_HAT_PIN_38 APL_GPIO_148 91 92 #define UP2_HAT_PIN_40_DEV APL_GPIO_DEV_W_0 93 #define UP2_HAT_PIN_40 APL_GPIO_149 94 95 #endif /* __INC_BOARD_H */ 96