1/*
2 * Copyright 2025 Variscite Ltd.
3 * Copyright 2021-2024 NXP
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8/dts-v1/;
9
10#include <nxp/nxp_mimx8mp_a53.dtsi>
11#include "imx8mp_var_dart-pinctrl.dtsi"
12#include <zephyr/dt-bindings/gpio/gpio.h>
13#include <zephyr/dt-bindings/input/input-event-codes.h>
14
15/ {
16	model = "Variscite DART-MX8M-PLUS A53";
17	compatible = "fsl,mimx8mp";
18
19	chosen {
20		zephyr,console = &uart3;
21		zephyr,shell-uart = &uart3;
22		/* sram node actually locates at DDR DRAM */
23		zephyr,sram = &dram;
24	};
25
26	cpus {
27		cpu@0 {
28			status = "disabled";
29		};
30
31		cpu@1 {
32			status = "disabled";
33		};
34
35		cpu@2 {
36			status = "disabled";
37		};
38	};
39
40	dram: memory@40480000 {
41		reg = <0x40480000 DT_SIZE_M(1)>;
42	};
43
44	soc {
45		uart3: uart@30880000 {
46			compatible = "nxp,imx-iuart";
47			reg = <0x30880000 DT_SIZE_K(64)>;
48			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
49			interrupt-names = "irq_0";
50			interrupt-parent = <&gic>;
51			clocks = <&ccm IMX_CCM_UART3_CLK 0x68 12>;
52			rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)|\
53				RDC_DOMAIN_PERM(M7_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>;
54			status = "okay";
55			current-speed = <115200>;
56			pinctrl-0 = <&uart3_default>;
57			pinctrl-names = "default";
58		};
59	};
60
61	aliases {
62		led0 = &blinky0;
63		sw0 = &button0;
64	};
65
66	leds {
67		compatible = "gpio-leds";
68
69		blinky0: blinky_0 {
70			gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
71		};
72	};
73
74	keys {
75		compatible = "gpio-keys";
76
77		button0: btn_0 {
78			label = "BTN0";
79			gpios = <&gpio3 8 (GPIO_PULL_UP|GPIO_ACTIVE_LOW)>;
80			zephyr,code = <INPUT_KEY_0>;
81		};
82	};
83};
84
85&gpio3 {
86	status = "okay";
87};
88