1 /* 2 * 3 * Copyright (c) 2017 Linaro Limited. 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 #ifndef ZEPHYR_DRIVERS_CLOCK_CONTROL_STM32_LL_CLOCK_H_ 9 #define ZEPHYR_DRIVERS_CLOCK_CONTROL_STM32_LL_CLOCK_H_ 10 11 #include <stdint.h> 12 13 #include <zephyr/device.h> 14 15 #include <stm32_ll_utils.h> 16 17 /* Macros to fill up multiplication and division factors values */ 18 #define z_pllm(v) LL_RCC_PLLM_DIV_ ## v 19 #define pllm(v) z_pllm(v) 20 21 #define z_pllp(v) LL_RCC_PLLP_DIV_ ## v 22 #define pllp(v) z_pllp(v) 23 24 #define z_pllq(v) LL_RCC_PLLQ_DIV_ ## v 25 #define pllq(v) z_pllq(v) 26 27 #define z_pllr(v) LL_RCC_PLLR_DIV_ ## v 28 #define pllr(v) z_pllr(v) 29 30 #if defined(RCC_PLLI2SCFGR_PLLI2SM) 31 /* Some stm32F4 devices have a dedicated PLL I2S with M divider */ 32 #define z_plli2s_m(v) LL_RCC_PLLI2SM_DIV_ ## v 33 #else 34 /* Some stm32F4 devices (typ. stm32F401) have a dedicated PLL I2S with PLL M divider */ 35 #define z_plli2s_m(v) LL_RCC_PLLM_DIV_ ## v 36 #endif /* RCC_PLLI2SCFGR_PLLI2SM */ 37 #define plli2sm(v) z_plli2s_m(v) 38 39 #define z_plli2s_q(v) LL_RCC_PLLI2SQ_DIV_ ## v 40 #define plli2sq(v) z_plli2s_q(v) 41 42 #define z_plli2s_r(v) LL_RCC_PLLI2SR_DIV_ ## v 43 #define plli2sr(v) z_plli2s_r(v) 44 45 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 46 #define z_pllsai1_m(v) LL_RCC_PLLSAI1M_DIV_ ## v 47 #else 48 #define z_pllsai1_m(v) LL_RCC_PLLM_DIV_ ## v 49 #endif 50 #define pllsai1m(v) z_pllsai1_m(v) 51 52 #define z_pllsai1_p(v) LL_RCC_PLLSAI1P_DIV_ ## v 53 #define pllsai1p(v) z_pllsai1_p(v) 54 55 #define z_pllsai1_q(v) LL_RCC_PLLSAI1Q_DIV_ ## v 56 #define pllsai1q(v) z_pllsai1_q(v) 57 58 #define z_pllsai1_r(v) LL_RCC_PLLSAI1R_DIV_ ## v 59 #define pllsai1r(v) z_pllsai1_r(v) 60 61 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 62 #define z_pllsai2_m(v) LL_RCC_PLLSAI2M_DIV_ ## v 63 #else 64 #define z_pllsai2_m(v) LL_RCC_PLLM_DIV_ ## v 65 #endif 66 #define pllsai2m(v) z_pllsai2_m(v) 67 68 #define z_pllsai2_p(v) LL_RCC_PLLSAI2P_DIV_ ## v 69 #define pllsai2p(v) z_pllsai2_p(v) 70 71 #define z_pllsai2_q(v) LL_RCC_PLLSAI2Q_DIV_ ## v 72 #define pllsai2q(v) z_pllsai2_q(v) 73 74 #define z_pllsai2_r(v) LL_RCC_PLLSAI2R_DIV_ ## v 75 #define pllsai2r(v) z_pllsai2_r(v) 76 77 #define z_pllsai2_divr(v) LL_RCC_PLLSAI2DIVR_DIV_ ## v 78 #define pllsai2divr(v) z_pllsai2_divr(v) 79 80 #ifdef __cplusplus 81 extern "C" { 82 #endif 83 84 #if defined(STM32_PLL_ENABLED) 85 void config_pll_sysclock(void); 86 uint32_t get_pllout_frequency(void); 87 uint32_t get_pllsrc_frequency(void); 88 #endif 89 #if defined(STM32_PLL2_ENABLED) 90 void config_pll2(void); 91 #endif 92 #if defined(STM32_PLLI2S_ENABLED) 93 void config_plli2s(void); 94 #endif 95 #if defined(STM32_PLLSAI1_ENABLED) 96 uint32_t get_pllsai1src_frequency(void); 97 void config_pllsai1(void); 98 #endif 99 #if defined(STM32_PLLSAI2_ENABLED) 100 uint32_t get_pllsai2src_frequency(void); 101 void config_pllsai2(void); 102 #endif 103 void config_enable_default_clocks(void); 104 void config_regulator_voltage(uint32_t hclk_freq); 105 int enabled_clock(uint32_t src_clk); 106 107 #if defined(STM32_CK48_ENABLED) 108 uint32_t get_ck48_frequency(void); 109 #endif 110 111 /* functions exported to the soc power.c */ 112 int stm32_clock_control_init(const struct device *dev); 113 void stm32_clock_control_standby_exit(void); 114 115 #ifdef __cplusplus 116 } 117 #endif 118 119 #endif /* ZEPHYR_DRIVERS_CLOCK_CONTROL_STM32_LL_CLOCK_H_ */ 120