1 /*
2 * Copyright (c) 2025, Linumiz GmbH
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT ti_mspm0_timer_counter
8
9 #include <zephyr/drivers/counter.h>
10 #include <zephyr/drivers/clock_control.h>
11 #include <zephyr/drivers/clock_control/mspm0_clock_control.h>
12 #include <zephyr/kernel.h>
13 #include <zephyr/device.h>
14 #include <zephyr/logging/log.h>
15
16 #include <ti/driverlib/dl_timera.h>
17 #include <ti/driverlib/dl_timerg.h>
18 #include <ti/driverlib/dl_timer.h>
19
20 LOG_MODULE_REGISTER(mspm0_counter, CONFIG_COUNTER_LOG_LEVEL);
21
22 struct counter_mspm0_data {
23 void *user_data_top;
24 void *user_data;
25 counter_top_callback_t top_cb;
26 counter_alarm_callback_t alarm_cb;
27 };
28
29 struct counter_mspm0_config {
30 struct counter_config_info counter_info;
31 GPTIMER_Regs *base;
32 const struct device *clock_dev;
33 const struct mspm0_sys_clock clock_subsys;
34 DL_Timer_ClockConfig clk_config;
35 void (*irq_config_func)(void);
36 };
37
counter_mspm0_start(const struct device * dev)38 static int counter_mspm0_start(const struct device *dev)
39 {
40 const struct counter_mspm0_config *config = dev->config;
41
42 DL_Timer_startCounter(config->base);
43
44 return 0;
45 }
46
counter_mspm0_stop(const struct device * dev)47 static int counter_mspm0_stop(const struct device *dev)
48 {
49 const struct counter_mspm0_config *config = dev->config;
50
51 DL_Timer_stopCounter(config->base);
52
53 return 0;
54 }
55
counter_mspm0_get_value(const struct device * dev,uint32_t * ticks)56 static int counter_mspm0_get_value(const struct device *dev, uint32_t *ticks)
57 {
58 const struct counter_mspm0_config *config = dev->config;
59
60 *ticks = DL_Timer_getTimerCount(config->base);
61
62 return 0;
63 }
64
counter_mspm0_set_top_value(const struct device * dev,const struct counter_top_cfg * cfg)65 static int counter_mspm0_set_top_value(const struct device *dev,
66 const struct counter_top_cfg *cfg)
67 {
68 const struct counter_mspm0_config *config = dev->config;
69 struct counter_mspm0_data *data = dev->data;
70
71 if (cfg->ticks > config->counter_info.max_top_value) {
72 return -ENOTSUP;
73 }
74
75 if (!(cfg->flags & COUNTER_TOP_CFG_DONT_RESET)) {
76 DL_Timer_stopCounter(config->base);
77 DL_Timer_startCounter(config->base);
78 } else if (DL_Timer_getTimerCount(config->base) >= cfg->ticks) {
79 if (cfg->flags & COUNTER_TOP_CFG_RESET_WHEN_LATE) {
80 DL_Timer_stopCounter(config->base);
81 DL_Timer_startCounter(config->base);
82 }
83
84 return -ETIME;
85 }
86
87 DL_Timer_setLoadValue(config->base, cfg->ticks);
88
89 data->top_cb = cfg->callback;
90 data->user_data_top = cfg->user_data;
91 if (cfg->callback) {
92 DL_Timer_clearInterruptStatus(config->base,
93 DL_TIMER_INTERRUPT_LOAD_EVENT);
94 DL_Timer_enableInterrupt(config->base,
95 DL_TIMER_INTERRUPT_LOAD_EVENT);
96 }
97
98 return 0;
99 }
100
counter_mspm0_get_top_value(const struct device * dev)101 static uint32_t counter_mspm0_get_top_value(const struct device *dev)
102 {
103 const struct counter_mspm0_config *config = dev->config;
104
105 return DL_Timer_getLoadValue(config->base);
106 }
107
counter_mspm0_set_alarm(const struct device * dev,uint8_t chan_id,const struct counter_alarm_cfg * alarm_cfg)108 static int counter_mspm0_set_alarm(const struct device *dev,
109 uint8_t chan_id,
110 const struct counter_alarm_cfg *alarm_cfg)
111 {
112 const struct counter_mspm0_config *config = dev->config;
113 struct counter_mspm0_data *data = dev->data;
114 uint32_t top = counter_mspm0_get_top_value(dev);
115 uint32_t ticks = alarm_cfg->ticks;
116
117 if (alarm_cfg->ticks > top) {
118 return -EINVAL;
119 }
120
121 if (data->alarm_cb != NULL) {
122 LOG_DBG("Alarm busy\n");
123 return -EBUSY;
124 }
125
126 if ((COUNTER_ALARM_CFG_ABSOLUTE & alarm_cfg->flags) == 0) {
127 ticks += DL_Timer_getTimerCount(config->base);
128 if (ticks > top) {
129 ticks %= top;
130 }
131 }
132
133 data->alarm_cb = alarm_cfg->callback;
134 data->user_data = alarm_cfg->user_data;
135
136 DL_Timer_setCaptureCompareValue(config->base, ticks,
137 DL_TIMER_CC_0_INDEX);
138 DL_Timer_clearInterruptStatus(config->base,
139 DL_TIMER_INTERRUPT_CC0_UP_EVENT);
140 DL_Timer_enableInterrupt(config->base,
141 DL_TIMER_INTERRUPT_CC0_UP_EVENT);
142
143 return 0;
144 }
145
counter_mspm0_cancel_alarm(const struct device * dev,uint8_t chan_id)146 static int counter_mspm0_cancel_alarm(const struct device *dev, uint8_t chan_id)
147 {
148 const struct counter_mspm0_config *config = dev->config;
149
150 DL_Timer_disableInterrupt(config->base,
151 DL_TIMER_INTERRUPT_CC0_UP_EVENT);
152
153 return 0;
154 }
155
counter_mspm0_get_pending_int(const struct device * dev)156 static uint32_t counter_mspm0_get_pending_int(const struct device *dev)
157 {
158 const struct counter_mspm0_config *config = dev->config;
159 uint32_t status;
160
161 status = DL_Timer_getRawInterruptStatus(config->base,
162 (DL_TIMER_INTERRUPT_LOAD_EVENT |
163 DL_TIMER_INTERRUPT_CC0_UP_EVENT));
164
165 return !!status;
166 }
167
counter_mspm0_get_freq(const struct device * dev)168 static uint32_t counter_mspm0_get_freq(const struct device *dev)
169 {
170 const struct counter_mspm0_config *config = dev->config;
171 DL_Timer_ClockConfig clkcfg;
172 uint32_t clock_rate;
173 int ret;
174
175 ret = clock_control_get_rate(config->clock_dev,
176 (clock_control_subsys_t)&config->clock_subsys,
177 &clock_rate);
178 if (ret != 0) {
179 LOG_ERR("clk get rate err %d", ret);
180 return 0;
181 }
182
183 DL_Timer_getClockConfig(config->base, &clkcfg);
184 clock_rate = clock_rate /
185 ((clkcfg.divideRatio + 1) * (clkcfg.prescale + 1));
186
187 return clock_rate;
188 }
189
counter_mspm0_init(const struct device * dev)190 static int counter_mspm0_init(const struct device *dev)
191 {
192 const struct counter_mspm0_config *config = dev->config;
193 DL_Timer_TimerConfig tim_config = {
194 .period = config->counter_info.max_top_value,
195 .timerMode = DL_TIMER_TIMER_MODE_PERIODIC_UP,
196 .startTimer = DL_TIMER_STOP,
197 };
198
199 if (!device_is_ready(config->clock_dev)) {
200 LOG_ERR("clock control device not ready");
201 return -ENODEV;
202 }
203
204 DL_Timer_reset(config->base);
205 if (!DL_Timer_isPowerEnabled(config->base)) {
206 DL_Timer_enablePower(config->base);
207 }
208
209 delay_cycles(CONFIG_MSPM0_PERIPH_STARTUP_DELAY);
210 DL_Timer_setClockConfig(config->base,
211 (DL_Timer_ClockConfig *)&config->clk_config);
212 DL_Timer_initTimerMode(config->base, &tim_config);
213 DL_Timer_setCounterRepeatMode(config->base,
214 DL_TIMER_REPEAT_MODE_ENABLED);
215
216 config->irq_config_func();
217
218 return 0;
219 }
220
221 static DEVICE_API(counter, mspm0_counter_api) = {
222 .start = counter_mspm0_start,
223 .stop = counter_mspm0_stop,
224 .get_value = counter_mspm0_get_value,
225 .set_top_value = counter_mspm0_set_top_value,
226 .get_pending_int = counter_mspm0_get_pending_int,
227 .get_top_value = counter_mspm0_get_top_value,
228 .get_freq = counter_mspm0_get_freq,
229 .cancel_alarm = counter_mspm0_cancel_alarm,
230 .set_alarm = counter_mspm0_set_alarm,
231 };
232
counter_mspm0_isr(void * arg)233 static void counter_mspm0_isr(void *arg)
234 {
235 const struct device *dev = (const struct device *)arg;
236 struct counter_mspm0_data *data = dev->data;
237 const struct counter_mspm0_config *config = dev->config;
238 uint32_t status;
239
240 status = DL_Timer_getPendingInterrupt(config->base);
241 if ((status == DL_TIMER_IIDX_CC0_UP) && data->alarm_cb) {
242 uint32_t now;
243 counter_alarm_callback_t alarm_cb = data->alarm_cb;
244
245 counter_mspm0_get_value(dev, &now);
246 data->alarm_cb = NULL;
247 alarm_cb(dev, 0, now, data->user_data);
248 } else if ((status == DL_TIMER_IIDX_LOAD) && data->top_cb) {
249 data->top_cb(dev, data->user_data_top);
250 }
251 }
252
253 #define MSPM0_COUNTER_IRQ_REGISTER(n) \
254 static void mspm0_ ## n ##_irq_register(void) \
255 { \
256 IRQ_CONNECT(DT_IRQN(DT_INST_PARENT(n)), \
257 DT_IRQ(DT_INST_PARENT(n), priority), \
258 counter_mspm0_isr, DEVICE_DT_INST_GET(n), 0); \
259 irq_enable(DT_IRQN(DT_INST_PARENT(n))); \
260 }
261
262 #define MSPM0_CLK_DIV(div) DT_CAT(DL_TIMER_CLOCK_DIVIDE_, div)
263
264 #define COUNTER_DEVICE_INIT_MSPM0(n) \
265 static struct counter_mspm0_data counter_mspm0_data_ ## n; \
266 MSPM0_COUNTER_IRQ_REGISTER(n) \
267 \
268 static const struct counter_mspm0_config counter_mspm0_config_ ## n = { \
269 .base = (GPTIMER_Regs *)DT_REG_ADDR(DT_INST_PARENT(n)), \
270 .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR_BY_IDX( \
271 DT_INST_PARENT(n), 0)), \
272 .clock_subsys = { \
273 .clk = DT_CLOCKS_CELL_BY_IDX(DT_INST_PARENT(n), 0, clk), \
274 }, \
275 .irq_config_func = (mspm0_ ## n ##_irq_register), \
276 .clk_config = { \
277 .clockSel = MSPM0_CLOCK_PERIPH_REG_MASK( \
278 DT_CLOCKS_CELL_BY_IDX(DT_INST_PARENT(n), 0, clk)), \
279 .divideRatio = MSPM0_CLK_DIV(DT_PROP(DT_INST_PARENT(n), \
280 ti_clk_div)), \
281 .prescale = DT_PROP(DT_INST_PARENT(n), ti_clk_prescaler), \
282 }, \
283 .counter_info = {.max_top_value = (DT_INST_PROP(n, resolution) == 32) \
284 ? UINT32_MAX : UINT16_MAX, \
285 .flags = COUNTER_CONFIG_INFO_COUNT_UP, \
286 .channels = 1}, \
287 }; \
288 \
289 DEVICE_DT_INST_DEFINE(n, \
290 counter_mspm0_init, \
291 NULL, \
292 &counter_mspm0_data_ ## n, \
293 &counter_mspm0_config_ ## n, \
294 POST_KERNEL, CONFIG_COUNTER_INIT_PRIORITY, \
295 &mspm0_counter_api);
296
297 DT_INST_FOREACH_STATUS_OKAY(COUNTER_DEVICE_INIT_MSPM0)
298