1 /*
2 * Copyright (c) 2017 Linaro Limited
3 * Copyright (c) 2017 BayLibre, SAS.
4 * Copyright (c) 2023 Google Inc
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9 #ifndef ZEPHYR_DRIVERS_FLASH_FLASH_STM32_H_
10 #define ZEPHYR_DRIVERS_FLASH_FLASH_STM32_H_
11
12 #include <zephyr/drivers/flash.h>
13 #include "stm32_hsem.h"
14
15 #if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_flash_controller), clocks) || \
16 DT_NODE_HAS_PROP(DT_INST(0, st_stm32h7_flash_controller), clocks)
17 #include <zephyr/drivers/clock_control.h>
18 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
19 #endif
20
21 /* Get the base address of the flash from the DTS node */
22 #define FLASH_STM32_BASE_ADDRESS DT_REG_ADDR(DT_INST(0, st_stm32_nv_flash))
23
24 struct flash_stm32_priv {
25 FLASH_TypeDef *regs;
26 #if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_flash_controller), clocks) || \
27 DT_NODE_HAS_PROP(DT_INST(0, st_stm32h7_flash_controller), clocks)
28 /* clock subsystem driving this peripheral */
29 struct stm32_pclken pclken;
30 #endif
31 struct k_sem sem;
32 };
33
34 #if DT_PROP(DT_INST(0, soc_nv_flash), write_block_size)
35 #define FLASH_STM32_WRITE_BLOCK_SIZE \
36 DT_PROP(DT_INST(0, soc_nv_flash), write_block_size)
37 #else
38 #error Flash write block size not available
39 /* Flash Write block size is extracted from device tree */
40 /* as flash node property 'write-block-size' */
41 #endif
42
43 #if defined(CONFIG_SOC_SERIES_STM32H5X)
44 /* FLASH register names differ for this serie */
45 #define FLASH_NSSR_BSY FLASH_SR_BSY
46 #define OPTR OPTCR
47 #endif /* CONFIG_SOC_SERIES_STM32H5X */
48
49 /* Register mapping for the stm32H7RS serie (single bank)*/
50 #if defined(CONFIG_SOC_SERIES_STM32H7RSX)
51 #define FLASH_NB_32BITWORD_IN_FLASHWORD 4 /* 128 bits */
52 #define CR1 CR
53 #define SR1 SR
54 /* flash sectore Nb [0-7] */
55 #define FLASH_CR_SNB FLASH_CR_SSN
56 #define FLASH_CR_SNB_Pos FLASH_CR_SSN_Pos
57 #define KEYR1 KEYR
58 #endif /* CONFIG_SOC_SERIES_STM32H7RSX */
59
60 /* Differentiate between arm trust-zone non-secure/secure, and others. */
61 #if defined(FLASH_NSSR_NSBSY) || defined(FLASH_NSSR_BSY) /* For mcu w. TZ in non-secure mode */
62 #define FLASH_SECURITY_NS
63 #define FLASH_STM32_SR NSSR
64 #elif defined(FLASH_SECSR_SECBSY) /* For mcu w. TZ in secured mode */
65 #error Flash is not supported in secure mode
66 #define FLASH_SECURITY_SEC
67 #else
68 #define FLASH_SECURITY_NA /* For series which does not have
69 * secured or non-secured mode
70 */
71 #define FLASH_STM32_SR SR
72 #endif
73
74 #define FLASH_STM32_PRIV(dev) ((struct flash_stm32_priv *)((dev)->data))
75 #define FLASH_STM32_REGS(dev) (FLASH_STM32_PRIV(dev)->regs)
76
77 /* Redefinitions of flags and masks to harmonize stm32 series: */
78 #if defined(CONFIG_SOC_SERIES_STM32U5X)
79 #define FLASH_STM32_NSLOCK FLASH_NSCR_LOCK
80 #define FLASH_STM32_DBANK FLASH_OPTR_DUALBANK
81 #define FLASH_STM32_NSPG FLASH_NSCR_PG
82 #define FLASH_STM32_NSBKER_MSK FLASH_NSCR_BKER_Msk
83 #define FLASH_STM32_NSBKER FLASH_NSCR_BKER
84 #define FLASH_STM32_NSPER FLASH_NSCR_PER
85 #define FLASH_STM32_NSPNB_MSK FLASH_NSCR_PNB_Msk
86 #define FLASH_STM32_NSPNB_POS FLASH_NSCR_PNB_Pos
87 #define FLASH_STM32_NSPNB FLASH_NSCR_PNB
88 #define FLASH_STM32_NSSTRT FLASH_NSCR_STRT
89 #define FLASH_PAGE_SIZE_128_BITS FLASH_PAGE_SIZE
90 #elif defined(CONFIG_SOC_SERIES_STM32U3X)
91 #define FLASH_STM32_NSLOCK FLASH_CR_LOCK
92 #define FLASH_STM32_DBANK FLASH_OPTR_DUALBANK
93 #define FLASH_STM32_NSPG FLASH_CR_PG
94 #define FLASH_STM32_NSBKER_MSK FLASH_CR_BKER_Msk
95 #define FLASH_STM32_NSBKER FLASH_CR_BKER
96 #define FLASH_STM32_NSPER FLASH_CR_PER
97 #define FLASH_STM32_NSPNB_MSK FLASH_CR_PNB_Msk
98 #define FLASH_STM32_NSPNB_POS FLASH_CR_PNB_Pos
99 #define FLASH_STM32_NSPNB FLASH_CR_PNB
100 #define FLASH_STM32_NSSTRT FLASH_CR_STRT
101 #define FLASH_PAGE_SIZE_128_BITS FLASH_PAGE_SIZE
102 #elif defined(CONFIG_SOC_SERIES_STM32H5X)
103 #define FLASH_OPTR_SWAP_BANK FLASH_OPTCR_SWAP_BANK
104 #define FLASH_STM32_NSLOCK FLASH_CR_LOCK
105 #define FLASH_STM32_DBANK 1
106 #define FLASH_STM32_NSPG FLASH_CR_PG
107 #define FLASH_STM32_NSBKER_MSK FLASH_CR_BKSEL_Msk
108 #define FLASH_STM32_NSBKER FLASH_CR_BKSEL
109 #define FLASH_STM32_NSPER FLASH_CR_SER
110 #define FLASH_STM32_NSPNB_MSK FLASH_CR_SNB_Msk
111 #define FLASH_STM32_NSPNB_POS FLASH_CR_SNB_Pos
112 #define FLASH_STM32_NSPNB FLASH_CR_PNB
113 #define FLASH_STM32_NSSTRT FLASH_CR_START
114 /* TODO: get values from the cmsis and stm32h5_hal_flash.h */
115 #undef FLASH_SIZE
116 /* Retrieve the FLASH SIZE from the DTS instead of cmsis as it seems erroneous */
117 #define FLASH_SIZE (CONFIG_FLASH_SIZE * 1024)
118 /* Values are redefined below from the stm32h5_hal_flash.h */
119 #define FLASH_PAGE_SIZE (FLASH_SECTOR_SIZE)
120 #define FLASH_PAGE_NB (FLASH_SECTOR_NB)
121 #define FLASH_PAGE_NB_PER_BANK (FLASH_BANK_SIZE / FLASH_PAGE_SIZE)
122 #define FLASH_PAGE_SIZE_128_BITS FLASH_PAGE_SIZE
123 #elif defined(CONFIG_SOC_SERIES_STM32L5X)
124 #define FLASH_STM32_NSLOCK FLASH_NSCR_NSLOCK
125 #define FLASH_STM32_NSPG FLASH_NSCR_NSPG
126 #define FLASH_STM32_NSBKER_MSK FLASH_NSCR_NSBKER_Pos
127 #define FLASH_STM32_NSBKER FLASH_NSCR_NSBKER
128 #define FLASH_STM32_NSPER FLASH_NSCR_NSPER
129 #define FLASH_STM32_NSPNB_MSK FLASH_NSCR_NSPNB_Msk
130 #define FLASH_STM32_NSPNB_POS FLASH_NSCR_NSPNB_Pos
131 #define FLASH_STM32_NSPNB FLASH_NSCR_NSPNB
132 #define FLASH_STM32_NSSTRT FLASH_NSCR_NSSTRT
133 #elif defined(CONFIG_SOC_SERIES_STM32WBAX)
134 #define NSCR NSCR1
135 #define FLASH_STM32_NSLOCK FLASH_NSCR1_LOCK
136 #define FLASH_STM32_NSPG FLASH_NSCR1_PG
137 #define FLASH_STM32_NSBKER_MSK FLASH_NSCR1_BKER_Msk
138 #define FLASH_STM32_NSBKER FLASH_NSCR1_BKER
139 #define FLASH_STM32_NSPER FLASH_NSCR1_PER
140 #define FLASH_STM32_NSPNB_MSK FLASH_NSCR1_PNB_Msk
141 #define FLASH_STM32_NSPNB_POS FLASH_NSCR1_PNB_Pos
142 #define FLASH_STM32_NSPNB FLASH_NSCR1_PNB
143 #define FLASH_STM32_NSSTRT FLASH_NSCR1_STRT
144 /* STM32WBA6x has DUAL bank flash */
145 #if defined(FLASH_OPTR_DUAL_BANK)
146 #define FLASH_STM32_DBANK FLASH_OPTR_DUAL_BANK
147 #endif /* FLASH_OPTR_DUAL_BANK */
148 #endif /* CONFIG_SOC_SERIES_STM32U5X */
149
150 #if defined(FLASH_OPTR_DBANK)
151 #define FLASH_STM32_DBANK FLASH_OPTR_DBANK
152 #endif /* FLASH_OPTR_DBANK */
153
154 #if defined(CONFIG_SOC_SERIES_STM32G0X)
155 #if defined(FLASH_FLAG_BSY2)
156 #define FLASH_STM32_SR_BUSY (FLASH_FLAG_BSY1 | FLASH_FLAG_BSY2);
157 #else
158 #define FLASH_STM32_SR_BUSY (FLASH_SR_BSY1)
159 #endif /* defined(FLASH_FLAG_BSY2) */
160 #else
161 #define FLASH_STM32_SR_BUSY (FLASH_FLAG_BSY)
162 #endif
163
164 #if defined(CONFIG_SOC_SERIES_STM32G0X)
165 #define FLASH_STM32_SR_CFGBSY (FLASH_SR_CFGBSY)
166 #elif defined(FLASH_FLAG_CFGBSY)
167 #define FLASH_STM32_SR_CFGBSY (FLASH_FLAG_CFGBSY)
168 #endif
169
170 #if defined(CONFIG_SOC_SERIES_STM32G0X)
171 /* STM32G0 HAL FLASH_FLAG_x don't represent bit-masks, need FLASH_SR_x instead */
172 #define FLASH_STM32_SR_OPERR FLASH_SR_OPERR
173 #define FLASH_STM32_SR_PGERR 0
174 #define FLASH_STM32_SR_PROGERR FLASH_SR_PROGERR
175 #define FLASH_STM32_SR_WRPERR FLASH_SR_WRPERR
176 #define FLASH_STM32_SR_PGAERR FLASH_SR_PGAERR
177 #define FLASH_STM32_SR_SIZERR FLASH_SR_SIZERR
178 #define FLASH_STM32_SR_PGSERR FLASH_SR_PGSERR
179 #define FLASH_STM32_SR_MISERR FLASH_SR_MISERR
180 #define FLASH_STM32_SR_FASTERR FLASH_SR_FASTERR
181 #if defined(FLASH_SR_RDERR)
182 #define FLASH_STM32_SR_RDERR FLASH_SR_RDERR
183 #else
184 #define FLASH_STM32_SR_RDERR 0
185 #endif
186 #define FLASH_STM32_SR_PGPERR 0
187
188 #else /* !defined(CONFIG_SOC_SERIES_STM32G0X) */
189 #if defined(FLASH_FLAG_OPERR)
190 #define FLASH_STM32_SR_OPERR FLASH_FLAG_OPERR
191 #else
192 #define FLASH_STM32_SR_OPERR 0
193 #endif
194
195 #if defined(FLASH_FLAG_PGERR)
196 #define FLASH_STM32_SR_PGERR FLASH_FLAG_PGERR
197 #else
198 #define FLASH_STM32_SR_PGERR 0
199 #endif
200
201 #if defined(FLASH_FLAG_PROGERR)
202 #define FLASH_STM32_SR_PROGERR FLASH_FLAG_PROGERR
203 #else
204 #define FLASH_STM32_SR_PROGERR 0
205 #endif
206
207 #if defined(FLASH_FLAG_WRPERR)
208 #define FLASH_STM32_SR_WRPERR FLASH_FLAG_WRPERR
209 #else
210 #define FLASH_STM32_SR_WRPERR 0
211 #endif
212
213 #if defined(FLASH_FLAG_PGAERR)
214 #define FLASH_STM32_SR_PGAERR FLASH_FLAG_PGAERR
215 #else
216 #define FLASH_STM32_SR_PGAERR 0
217 #endif
218
219 #if defined(FLASH_FLAG_SIZERR)
220 #define FLASH_STM32_SR_SIZERR FLASH_FLAG_SIZERR
221 #else
222 #define FLASH_STM32_SR_SIZERR 0
223 #endif
224
225 #if defined(FLASH_FLAG_PGSERR)
226 #define FLASH_STM32_SR_PGSERR FLASH_FLAG_PGSERR
227 #else
228 #define FLASH_STM32_SR_PGSERR 0
229 #endif
230
231 #if defined(FLASH_FLAG_MISERR)
232 #define FLASH_STM32_SR_MISERR FLASH_FLAG_MISERR
233 #else
234 #define FLASH_STM32_SR_MISERR 0
235 #endif
236
237 #if defined(FLASH_FLAG_FASTERR)
238 #define FLASH_STM32_SR_FASTERR FLASH_FLAG_FASTERR
239 #else
240 #define FLASH_STM32_SR_FASTERR 0
241 #endif
242
243 #if defined(FLASH_FLAG_RDERR)
244 #define FLASH_STM32_SR_RDERR FLASH_FLAG_RDERR
245 #else
246 #define FLASH_STM32_SR_RDERR 0
247 #endif
248
249 #if defined(FLASH_FLAG_PGPERR)
250 #define FLASH_STM32_SR_PGPERR FLASH_FLAG_PGPERR
251 #else
252 #define FLASH_STM32_SR_PGPERR 0
253 #endif
254
255 #endif /* !defined(CONFIG_SOC_SERIES_STM32G0X) */
256
257 #define FLASH_STM32_SR_ERRORS (FLASH_STM32_SR_OPERR | \
258 FLASH_STM32_SR_PGERR | \
259 FLASH_STM32_SR_PROGERR | \
260 FLASH_STM32_SR_WRPERR | \
261 FLASH_STM32_SR_PGAERR | \
262 FLASH_STM32_SR_SIZERR | \
263 FLASH_STM32_SR_PGSERR | \
264 FLASH_STM32_SR_MISERR | \
265 FLASH_STM32_SR_FASTERR | \
266 FLASH_STM32_SR_RDERR | \
267 FLASH_STM32_SR_PGPERR)
268
269 #define FLASH_STM32_RDP0 0xAA
270 #define FLASH_STM32_RDP2 0xCC
271 #define FLASH_STM32_RDP1 \
272 DT_PROP(DT_INST(0, st_stm32_flash_controller), st_rdp1_enable_byte)
273
274 #if FLASH_STM32_RDP1 == FLASH_STM32_RDP0 || FLASH_STM32_RDP1 == FLASH_STM32_RDP2
275 #error RDP1 byte has to be different than RDP0 and RDP2 byte
276 #endif
277
278 #ifdef CONFIG_FLASH_PAGE_LAYOUT
flash_stm32_range_exists(const struct device * dev,off_t offset,uint32_t len)279 static inline bool flash_stm32_range_exists(const struct device *dev,
280 off_t offset,
281 uint32_t len)
282 {
283 struct flash_pages_info info;
284
285 return !(flash_get_page_info_by_offs(dev, offset, &info) ||
286 flash_get_page_info_by_offs(dev, offset + len - 1, &info));
287 }
288 #endif /* CONFIG_FLASH_PAGE_LAYOUT */
289
290
291 #if defined(CONFIG_MULTITHREADING) || defined(CONFIG_STM32H7_DUAL_CORE)
292 /*
293 * This is named flash_stm32_sem_take instead of flash_stm32_lock (and
294 * similarly for flash_stm32_sem_give) to avoid confusion with locking
295 * actual flash pages.
296 */
297
_flash_stm32_sem_take(const struct device * dev)298 static inline void _flash_stm32_sem_take(const struct device *dev)
299 {
300 k_sem_take(&FLASH_STM32_PRIV(dev)->sem, K_FOREVER);
301 z_stm32_hsem_lock(CFG_HW_FLASH_SEMID, HSEM_LOCK_WAIT_FOREVER);
302 }
303
_flash_stm32_sem_give(const struct device * dev)304 static inline void _flash_stm32_sem_give(const struct device *dev)
305 {
306 z_stm32_hsem_unlock(CFG_HW_FLASH_SEMID);
307 k_sem_give(&FLASH_STM32_PRIV(dev)->sem);
308 }
309
310 #define flash_stm32_sem_init(dev) k_sem_init(&FLASH_STM32_PRIV(dev)->sem, 1, 1)
311 #define flash_stm32_sem_take(dev) _flash_stm32_sem_take(dev)
312 #define flash_stm32_sem_give(dev) _flash_stm32_sem_give(dev)
313 #else
314 #define flash_stm32_sem_init(dev)
315 #define flash_stm32_sem_take(dev)
316 #define flash_stm32_sem_give(dev)
317 #endif /* CONFIG_MULTITHREADING */
318
319 #ifdef CONFIG_FLASH_EX_OP_ENABLED
320 int flash_stm32_ex_op(const struct device *dev, uint16_t code,
321 const uintptr_t in, void *out);
322 #endif /* CONFIG_FLASH_EX_OP_ENABLED */
323
flash_stm32_valid_write(off_t offset,uint32_t len)324 static inline bool flash_stm32_valid_write(off_t offset, uint32_t len)
325 {
326 return ((offset % FLASH_STM32_WRITE_BLOCK_SIZE == 0) &&
327 (len % FLASH_STM32_WRITE_BLOCK_SIZE == 0U));
328 }
329
330 bool flash_stm32_valid_range(const struct device *dev, off_t offset,
331 uint32_t len, bool write);
332
333 int flash_stm32_write_range(const struct device *dev, unsigned int offset,
334 const void *data, unsigned int len);
335
336 int flash_stm32_block_erase_loop(const struct device *dev,
337 unsigned int offset,
338 unsigned int len);
339
340 int flash_stm32_wait_flash_idle(const struct device *dev);
341
342 uint32_t flash_stm32_option_bytes_read(const struct device *dev);
343
344 int flash_stm32_option_bytes_write(const struct device *dev, uint32_t mask,
345 uint32_t value);
346
347 int flash_stm32_cr_lock(const struct device *dev, bool enable);
348
349 #ifdef CONFIG_SOC_SERIES_STM32WBX
350 int flash_stm32_check_status(const struct device *dev);
351 #endif /* CONFIG_SOC_SERIES_STM32WBX */
352
353 #ifdef CONFIG_FLASH_PAGE_LAYOUT
354 void flash_stm32_page_layout(const struct device *dev,
355 const struct flash_pages_layout **layout,
356 size_t *layout_size);
357 #endif
358
359 #if defined(CONFIG_FLASH_STM32_WRITE_PROTECT)
360
361 int flash_stm32_update_wp_sectors(const struct device *dev,
362 uint64_t changed_sectors,
363 uint64_t protected_sectors);
364
365 int flash_stm32_get_wp_sectors(const struct device *dev,
366 uint64_t *protected_sectors);
367 #endif
368 #if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION)
369 uint8_t flash_stm32_get_rdp_level(const struct device *dev);
370
371 void flash_stm32_set_rdp_level(const struct device *dev, uint8_t level);
372 #endif
373
374 #if defined(CONFIG_FLASH_STM32_BLOCK_REGISTERS)
375 int flash_stm32_control_register_disable(const struct device *dev);
376 int flash_stm32_option_bytes_disable(const struct device *dev);
377 #endif
378
379 #endif /* ZEPHYR_DRIVERS_FLASH_FLASH_STM32_H_ */
380