1 /*
2 * Copyright (c) 2024 Analog Devices, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT adi_max32_i2c
8
9 #include <errno.h>
10 #include <zephyr/drivers/i2c.h>
11 #include <zephyr/drivers/i2c/rtio.h>
12 #include <zephyr/drivers/pinctrl.h>
13 #include <zephyr/kernel.h>
14 #include <zephyr/drivers/clock_control/adi_max32_clock_control.h>
15 #include <zephyr/irq.h>
16
17 #include <wrap_max32_i2c.h>
18
19 #include <zephyr/logging/log.h>
20 LOG_MODULE_REGISTER(max32_i2c);
21
22 #define ADI_MAX32_I2C_INT_FL0_MASK 0x00FFFFFF
23 #define ADI_MAX32_I2C_INT_FL1_MASK 0x7
24
25 #define ADI_MAX32_I2C_STATUS_MASTER_BUSY BIT(5)
26
27 #define I2C_RECOVER_MAX_RETRIES 3
28 #define I2C_STANDAR_BITRATE_CLKHI 0x12b
29
30 static int complete_flag;
31
32 /* Driver config */
33 struct max32_i2c_config {
34 mxc_i2c_regs_t *regs;
35 const struct pinctrl_dev_config *pctrl;
36 const struct device *clock;
37 struct max32_perclk perclk;
38 uint32_t bitrate;
39 #if defined(CONFIG_I2C_MAX32_INTERRUPT)
40 uint8_t irqn;
41 void (*irq_config_func)(const struct device *dev);
42 #endif
43 };
44
45 struct max32_i2c_data {
46 mxc_i2c_req_t req;
47 const struct device *dev;
48 uint8_t target_mode;
49 uint8_t flags;
50 struct i2c_rtio *ctx;
51 uint32_t readb;
52 uint32_t written;
53 uint8_t second_msg_flag;
54 #if defined(CONFIG_I2C_MAX32_INTERRUPT)
55 int err;
56 #endif
57 };
58
max32_configure(const struct device * dev,uint32_t dev_cfg)59 static int max32_configure(const struct device *dev,
60 uint32_t dev_cfg)
61 {
62 struct i2c_rtio *const ctx = ((struct max32_i2c_data *)
63 dev->data)->ctx;
64
65 return i2c_rtio_configure(ctx, dev_cfg);
66 }
67
max32_do_configure(const struct device * dev,uint32_t dev_cfg)68 static int max32_do_configure(const struct device *dev, uint32_t dev_cfg)
69 {
70 int ret = 0;
71 const struct max32_i2c_config *const cfg = dev->config;
72 mxc_i2c_regs_t *i2c = cfg->regs;
73
74 switch (I2C_SPEED_GET(dev_cfg)) {
75 case I2C_SPEED_STANDARD: /** I2C Standard Speed: 100 kHz */
76 ret = MXC_I2C_SetFrequency(i2c, MXC_I2C_STD_MODE);
77 break;
78
79 case I2C_SPEED_FAST: /** I2C Fast Speed: 400 kHz */
80 ret = MXC_I2C_SetFrequency(i2c, MXC_I2C_FAST_SPEED);
81 break;
82
83 #if defined(MXC_I2C_FASTPLUS_SPEED)
84 case I2C_SPEED_FAST_PLUS: /** I2C Fast Plus Speed: 1 MHz */
85 ret = MXC_I2C_SetFrequency(i2c, MXC_I2C_FASTPLUS_SPEED);
86 break;
87 #endif
88
89 #if defined(MXC_I2C_HIGH_SPEED)
90 case I2C_SPEED_HIGH: /** I2C High Speed: 3.4 MHz */
91 ret = MXC_I2C_SetFrequency(i2c, MXC_I2C_HIGH_SPEED);
92 break;
93 #endif
94
95 default:
96 /* Speed not supported */
97 return -ENOTSUP;
98 }
99
100 return ((ret > 0) ? 0 : -EIO);
101 }
102
103 static void max32_complete(const struct device *dev, int status);
104
max32_msg_start(const struct device * dev,uint8_t flags,uint8_t * buf,size_t buf_len,uint16_t i2c_addr)105 static int max32_msg_start(const struct device *dev, uint8_t flags,
106 uint8_t *buf, size_t buf_len, uint16_t i2c_addr)
107 {
108 int ret = 0;
109 const struct max32_i2c_config *const cfg = dev->config;
110 struct max32_i2c_data *data = dev->data;
111 mxc_i2c_regs_t *i2c = cfg->regs;
112 mxc_i2c_req_t *req = &data->req;
113 uint8_t target_rw;
114
115 req->i2c = i2c;
116 req->addr = i2c_addr;
117
118 if (data->second_msg_flag == 0) {
119 MXC_I2C_ClearRXFIFO(i2c);
120 MXC_I2C_ClearTXFIFO(i2c);
121 MXC_I2C_SetRXThreshold(i2c, 1);
122
123 /* First message should always begin with a START condition */
124 flags |= I2C_MSG_RESTART;
125 }
126
127 if (flags & I2C_MSG_READ) {
128 req->rx_buf = (unsigned char *)buf;
129 req->rx_len = buf_len;
130 req->tx_buf = NULL;
131 req->tx_len = 0;
132 target_rw = (i2c_addr << 1) | 0x1;
133 } else {
134 req->tx_buf = (unsigned char *)buf;
135 req->tx_len = buf_len;
136 req->rx_buf = NULL;
137 req->rx_len = 0;
138 target_rw = (i2c_addr << 1) & ~0x1;
139 }
140 data->flags = flags;
141 data->readb = 0;
142 data->written = 0;
143 data->err = 0;
144
145 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK);
146 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_ERR, 0);
147 Wrap_MXC_I2C_SetRxCount(i2c, req->rx_len);
148 if ((data->flags & I2C_MSG_RESTART)) {
149 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_ADDR_ACK, 0);
150 MXC_I2C_Start(i2c);
151 Wrap_MXC_I2C_WaitForRestart(i2c);
152 MXC_I2C_WriteTXFIFO(i2c, &target_rw, 1);
153 } else {
154 if (req->tx_len) {
155 data->written = MXC_I2C_WriteTXFIFO(i2c, req->tx_buf, 1);
156 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_TX_THD, 0);
157 } else {
158 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_RX_THD, 0);
159 }
160 }
161
162 if (data->err) {
163 MXC_I2C_Stop(i2c);
164 ret = data->err;
165 }
166
167 return ret;
168 }
169
max32_transfer(const struct device * dev,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t target_address)170 static int max32_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
171 uint16_t target_address)
172 {
173 struct i2c_rtio *const ctx = ((struct max32_i2c_data *)
174 dev->data)->ctx;
175 ((struct max32_i2c_data *)dev->data)->second_msg_flag = 0;
176
177 return i2c_rtio_transfer(ctx, msgs, num_msgs, target_address);
178 }
179
180
181
i2c_max32_isr_controller(const struct device * dev,mxc_i2c_regs_t * i2c)182 static void i2c_max32_isr_controller(const struct device *dev, mxc_i2c_regs_t *i2c)
183 {
184 struct max32_i2c_data *data = dev->data;
185 mxc_i2c_req_t *req = &data->req;
186 uint32_t written, readb;
187 uint32_t txfifolevel;
188 uint32_t int_fl0, int_fl1;
189 uint32_t int_en0, int_en1;
190
191 written = data->written;
192 readb = data->readb;
193
194 Wrap_MXC_I2C_GetIntEn(i2c, &int_en0, &int_en1);
195 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
196 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK);
197 txfifolevel = Wrap_MXC_I2C_GetTxFIFOLevel(i2c);
198
199 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ERR) {
200 data->err = -EIO;
201 Wrap_MXC_I2C_SetIntEn(i2c, 0, 0);
202 max32_complete(dev, data->err);
203 return;
204 }
205
206 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ADDR_ACK) {
207 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_ADDR_ACK, 0);
208 if (written < req->tx_len) {
209 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_TX_THD, 0);
210 } else if (readb < req->rx_len) {
211 MXC_I2C_EnableInt(
212 i2c, ADI_MAX32_I2C_INT_EN0_RX_THD | ADI_MAX32_I2C_INT_EN0_DONE, 0);
213 }
214 }
215
216 if (req->tx_len &&
217 (int_fl0 & (ADI_MAX32_I2C_INT_FL0_TX_THD | ADI_MAX32_I2C_INT_FL0_DONE))) {
218 if (written < req->tx_len) {
219 written += MXC_I2C_WriteTXFIFO(i2c, &req->tx_buf[written],
220 req->tx_len - written);
221 } else {
222 if (!(int_en0 & ADI_MAX32_I2C_INT_EN0_DONE)) {
223 /* We are done, stop sending more data */
224 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_TX_THD, 0);
225 if (data->flags & I2C_MSG_STOP) {
226 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0);
227 /* Done flag is not set if stop/restart is not set */
228 Wrap_MXC_I2C_Stop(i2c);
229 } else {
230 complete_flag++;
231 }
232 }
233
234 if ((int_fl0 & ADI_MAX32_I2C_INT_FL0_DONE)) {
235 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0);
236 complete_flag++;
237 }
238 }
239 } else if ((int_fl0 & (ADI_MAX32_I2C_INT_FL0_RX_THD | ADI_MAX32_I2C_INT_FL0_DONE))) {
240 readb += MXC_I2C_ReadRXFIFO(i2c, &req->rx_buf[readb], req->rx_len - readb);
241 if (readb == req->rx_len) {
242 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_RX_THD, 0);
243 if (data->flags & I2C_MSG_STOP) {
244 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0);
245 Wrap_MXC_I2C_Stop(i2c);
246 complete_flag++;
247 } else {
248 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_DONE) {
249 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0);
250 }
251 }
252 } else if ((int_en0 & ADI_MAX32_I2C_INT_EN0_DONE) &&
253 (int_fl0 & ADI_MAX32_I2C_INT_FL0_DONE)) {
254 MXC_I2C_DisableInt(
255 i2c, (ADI_MAX32_I2C_INT_EN0_RX_THD | ADI_MAX32_I2C_INT_EN0_DONE),
256 0);
257 Wrap_MXC_I2C_SetRxCount(i2c, req->rx_len - readb);
258 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_ADDR_ACK, 0);
259 i2c->fifo = (req->addr << 1) | 0x1;
260 Wrap_MXC_I2C_Restart(i2c);
261 }
262 }
263 data->written = written;
264 data->readb = readb;
265
266 if (complete_flag == 1) {
267 max32_complete(dev, 0);
268 complete_flag = 0;
269 }
270 }
271
max32_start(const struct device * dev)272 static bool max32_start(const struct device *dev)
273 {
274 struct max32_i2c_data *data = dev->data;
275 struct i2c_rtio *ctx = data->ctx;
276 struct rtio_sqe *sqe = &ctx->txn_curr->sqe;
277 struct i2c_dt_spec *dt_spec = sqe->iodev->data;
278 int res = 0;
279
280 switch (sqe->op) {
281 case RTIO_OP_RX:
282 return max32_msg_start(dev, I2C_MSG_READ | sqe->iodev_flags,
283 sqe->rx.buf, sqe->rx.buf_len, dt_spec->addr);
284 case RTIO_OP_TINY_TX:
285 data->second_msg_flag = 0;
286 return max32_msg_start(dev, I2C_MSG_WRITE | sqe->iodev_flags,
287 (uint8_t *)sqe->tiny_tx.buf, sqe->tiny_tx.buf_len,
288 dt_spec->addr);
289 case RTIO_OP_TX:
290 return max32_msg_start(dev, I2C_MSG_WRITE | sqe->iodev_flags,
291 (uint8_t *)sqe->tx.buf, sqe->tx.buf_len,
292 dt_spec->addr);
293 case RTIO_OP_I2C_CONFIGURE:
294 res = max32_do_configure(dev, sqe->i2c_config);
295 return i2c_rtio_complete(data->ctx, res);
296 default:
297 LOG_ERR("Invalid op code %d for submission %p\n", sqe->op, (void *)sqe);
298 return i2c_rtio_complete(data->ctx, -EINVAL);
299 }
300 }
301
max32_complete(const struct device * dev,int status)302 static void max32_complete(const struct device *dev, int status)
303 {
304 struct max32_i2c_data *data = dev->data;
305 struct i2c_rtio *const ctx = data->ctx;
306 const struct max32_i2c_config *const cfg = dev->config;
307
308 if (cfg->regs->clkhi == I2C_STANDAR_BITRATE_CLKHI) {
309 /* When I2C is configured in Standard Bitrate 100KHz
310 * Hardware completes first read sample transaction
311 * and gets stuck in idle instead of starting the
312 * next transaction, if given k_busy_wait for
313 * 20 us ~= 2 additional I2C cycles sample read
314 * won't have any issues but all other transactions
315 * (like setup of sensor) will have this unnecessary
316 * delay. This doesn't happen when using Fast
317 * Bitrate 400Hz.
318 */
319 LOG_ERR("For Standard speed HW needs more time to run");
320 return;
321 }
322
323 if (i2c_rtio_complete(ctx, status)) {
324 data->second_msg_flag = 1;
325 max32_start(dev);
326 } else {
327 data->second_msg_flag = 0;
328 }
329 }
330
max32_submit(const struct device * dev,struct rtio_iodev_sqe * iodev_sqe)331 static void max32_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe)
332 {
333 struct max32_i2c_data *data = dev->data;
334 struct i2c_rtio *const ctx = data->ctx;
335
336 if (i2c_rtio_submit(ctx, iodev_sqe)) {
337 max32_start(dev);
338 }
339 }
340
341
i2c_max32_isr(const struct device * dev)342 static void i2c_max32_isr(const struct device *dev)
343 {
344 const struct max32_i2c_config *cfg = dev->config;
345 struct max32_i2c_data *data = dev->data;
346 mxc_i2c_regs_t *i2c = cfg->regs;
347
348 if (data->target_mode == 0) {
349 i2c_max32_isr_controller(dev, i2c);
350 return;
351 }
352 }
353
i2c_max32_init(const struct device * dev)354 static int i2c_max32_init(const struct device *dev)
355 {
356 const struct max32_i2c_config *const cfg = dev->config;
357 struct max32_i2c_data *data = dev->data;
358 mxc_i2c_regs_t *i2c = cfg->regs;
359 int ret = 0;
360
361 if (!device_is_ready(cfg->clock)) {
362 return -ENODEV;
363 }
364
365 MXC_I2C_Shutdown(i2c); /* Clear everything out */
366
367 ret = clock_control_on(cfg->clock, (clock_control_subsys_t)&cfg->perclk);
368 if (ret) {
369 return ret;
370 }
371
372 ret = pinctrl_apply_state(cfg->pctrl, PINCTRL_STATE_DEFAULT);
373 if (ret) {
374 return ret;
375 }
376
377 ret = MXC_I2C_Init(i2c, 1, 0); /* Configure as master */
378 if (ret) {
379 return ret;
380 }
381
382 MXC_I2C_SetFrequency(i2c, cfg->bitrate);
383
384 #if defined(CONFIG_I2C_MAX32_INTERRUPT)
385 cfg->irq_config_func(dev);
386 #endif
387
388 #ifdef CONFIG_I2C_MAX32_INTERRUPT
389 irq_enable(cfg->irqn);
390
391 #endif
392
393 data->dev = dev;
394
395 i2c_rtio_init(data->ctx, dev);
396 return ret;
397 }
398
399 static const struct i2c_driver_api max32_driver_api = {
400 .configure = max32_configure,
401 .transfer = max32_transfer,
402 .iodev_submit = max32_submit,
403 };
404
405 #if defined(CONFIG_I2C_TARGET) || defined(CONFIG_I2C_MAX32_INTERRUPT)
406 #define I2C_MAX32_CONFIG_IRQ_FUNC(n) \
407 .irq_config_func = i2c_max32_irq_config_func_##n, .irqn = DT_INST_IRQN(n),
408
409 #define I2C_MAX32_IRQ_CONFIG_FUNC(n) \
410 static void i2c_max32_irq_config_func_##n(const struct device *dev) \
411 { \
412 IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), i2c_max32_isr, \
413 DEVICE_DT_INST_GET(n), 0); \
414 }
415 #else
416 #define I2C_MAX32_CONFIG_IRQ_FUNC(n)
417 #define I2C_MAX32_IRQ_CONFIG_FUNC(n)
418 #endif
419
420
421 #define DEFINE_I2C_MAX32(_num) \
422 PINCTRL_DT_INST_DEFINE(_num); \
423 I2C_MAX32_IRQ_CONFIG_FUNC(_num) \
424 static const struct max32_i2c_config max32_i2c_dev_cfg_##_num = { \
425 .regs = (mxc_i2c_regs_t *)DT_INST_REG_ADDR(_num), \
426 .pctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(_num), \
427 .clock = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(_num)), \
428 .perclk.bus = DT_INST_CLOCKS_CELL(_num, offset), \
429 .perclk.bit = DT_INST_CLOCKS_CELL(_num, bit), \
430 .bitrate = DT_INST_PROP(_num, clock_frequency), \
431 I2C_MAX32_CONFIG_IRQ_FUNC(_num)}; \
432 I2C_RTIO_DEFINE(_i2c##n##_max32_rtio, \
433 DT_INST_PROP_OR(n, sq_size, CONFIG_I2C_RTIO_SQ_SIZE), \
434 DT_INST_PROP_OR(n, cq_size, CONFIG_I2C_RTIO_CQ_SIZE)); \
435 static struct max32_i2c_data max32_i2c_data_##_num = { \
436 .ctx = &CONCAT(_i2c, n, _max32_rtio), \
437 }; \
438 I2C_DEVICE_DT_INST_DEFINE(_num, i2c_max32_init, NULL, &max32_i2c_data_##_num, \
439 &max32_i2c_dev_cfg_##_num, PRE_KERNEL_2, \
440 CONFIG_I2C_INIT_PRIORITY, &max32_driver_api);
441
442 DT_INST_FOREACH_STATUS_OKAY(DEFINE_I2C_MAX32)
443