1# Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
2# SPDX-License-Identifier: Apache-2.0
3
4config CLIC
5	bool "RISC-V Core Local Interrupt Controller (CLIC)"
6	default y
7	depends on DT_HAS_NUCLEI_ECLIC_ENABLED || DT_HAS_RISCV_CLIC_ENABLED
8	select RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING
9	help
10	  Core Local Interrupt Controller provide low-latency, vectored,
11	  preemptive interrupts for RISC-V systems.
12
13config NUCLEI_ECLIC
14	bool "Enhanced Core Local Interrupt Controller (ECLIC)"
15	default y
16	depends on DT_HAS_NUCLEI_ECLIC_ENABLED
17	select CLIC
18	select CLIC_SMCLICSHV_EXT if RISCV_VECTORED_MODE
19	select CLIC_SMCLICCONFIG_EXT
20	select LEGACY_CLIC_MEMORYMAP_ACCESS
21	help
22	  Interrupt controller for Nuclei SoC core.
23
24config NRFX_CLIC
25	bool "VPR Core Local Interrpt Controller (CLIC)"
26	default y
27	depends on DT_HAS_NORDIC_NRF_CLIC_ENABLED
28	select GEN_IRQ_VECTOR_TABLE
29	help
30	  Interrupt controller for Nordic VPR cores.
31
32if CLIC
33
34config CLIC_SMCLICSHV_EXT
35	bool
36	help
37	  The selective hardware vectoring extension gives users the flexibility
38	  to select the behavior for each interrupt. The CLIC driver needs to
39	  implement the riscv_clic_irq_vector_set() function.
40
41config CLIC_SMCLICCONFIG_EXT
42	bool
43	help
44	  Enables the SMCLICCONFIG extension, allowing configuration of CLIC
45	  parameters such as the number of interrupt level bits.
46
47config CLIC_PARAMETER_INTCTLBITS
48	int "The number of modifiable bits in the clicintctl registers"
49	range 0 8
50	default 8
51	help
52	  This option specifies the number of modifiable bits in the clicintctl
53	  registers.
54
55config CLIC_PARAMETER_MNLBITS
56	int "The number of bits in CLICINTCTLBITS to encode the interrupt level"
57	range 0 CLIC_PARAMETER_INTCTLBITS
58	default 0
59	help
60	  This option specifies the number of bits in CLICINTCTLBITS assigned to
61	  encode the interrupt level at machine mode.
62
63config LEGACY_CLIC_MEMORYMAP_ACCESS
64	bool
65	help
66	  Enables legacy CLIC, allowing access to CLIC registers through
67	  memory-mapped access instead of indirect CSR access.
68
69config LEGACY_CLIC
70	bool "Use the legacy clic specification"
71	depends on RISCV_HAS_CLIC
72	help
73	  Enables legacy clic, where smclicshv extension is not supported and
74	  hardware vectoring is set via mode bits of mtvec.
75
76endif # CLIC
77