1 /*
2  * Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
3  * Copyright (c) 2025 Andes Technology Corporation
4  *
5  * SPDX-License-Identifier: Apache-2.0
6  */
7 
8 #ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_CLIC_H_
9 #define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_CLIC_H_
10 
11 /* CLIC relative CSR number */
12 #define CSR_MTVT       (0x307)
13 #define CSR_MNXTI      (0x345)
14 #define CSR_MINTTHRESH (0x347)
15 #define CSR_MISELECT   (0x350)
16 #define CSR_MIREG      (0x351)
17 #define CSR_MIREG2     (0x352)
18 
19 #ifndef __ASSEMBLER__
20 
21 #include <stddef.h>
22 
23 #ifdef CONFIG_LEGACY_CLIC_MEMORYMAP_ACCESS
24 /* CLIC Memory mapped register offset */
25 #define CLIC_CFG          (0x0)
26 #define CLIC_CTRL(irq)    (0x1000 + 4 * (irq))
27 #define CLIC_INTIP(irq)   (CLIC_CTRL(irq) + offsetof(union CLICCTRL, w.INTIP))
28 #define CLIC_INTIE(irq)   (CLIC_CTRL(irq) + offsetof(union CLICCTRL, w.INTIE))
29 #define CLIC_INTATTR(irq) (CLIC_CTRL(irq) + offsetof(union CLICCTRL, w.INTATTR))
30 #define CLIC_INTCTRL(irq) (CLIC_CTRL(irq) + offsetof(union CLICCTRL, w.INTCTRL))
31 #else
32 /* Indirect CSR Access miselect offset */
33 #define CLIC_CFG          (0x14A0)
34 #define CLIC_CTRL(irq)    (0x0) /* Dummy value for driver compatibility */
35 #define CLIC_INTIP(irq)   (0x1400 + (irq) / 32)
36 #define CLIC_INTIE(irq)   (0x1400 + (irq) / 32)
37 #define CLIC_INTATTR(irq) (0x1000 + (irq) / 4)
38 #define CLIC_INTCTRL(irq) (0x1000 + (irq) / 4)
39 #endif /* !CONFIG_LEGACY_CLIC_MEMORYMAP_ACCESS */
40 
41 /* Nuclei ECLIC memory mapped register offset */
42 #define CLIC_INFO (0x4)
43 #define CLIC_MTH  (0x8)
44 
45 /* CLIC register structure */
46 union CLICCFG {
47 	struct {
48 #ifdef CONFIG_NUCLEI_ECLIC
49 		uint32_t _reserved0: 1;
50 #endif /* CONFIG_NUCLEI_ECLIC */
51 		/** number of interrupt level bits */
52 		uint32_t nlbits: 4;
53 		/** number of clicintattr[i].MODE bits */
54 		uint32_t nmbits: 2;
55 		uint32_t _reserved1: 25;
56 	} w;
57 	uint32_t qw;
58 };
59 
60 union CLICINTIP {
61 	struct {
62 		/** Interrupt Pending */
63 		uint8_t IP: 1;
64 		uint8_t reserved0: 7;
65 	} b;
66 	uint8_t w;
67 };
68 
69 union CLICINTIE {
70 	struct {
71 		/** Interrupt Enabled */
72 		uint8_t IE: 1;
73 		uint8_t reserved0: 7;
74 	} b;
75 	uint8_t w;
76 };
77 
78 union CLICINTATTR {
79 	struct {
80 		/** 0: non-vectored 1:vectored */
81 		uint8_t shv: 1;
82 		/** 0: level 1: rising edge 2: falling edge */
83 		uint8_t trg: 2;
84 		uint8_t reserved0: 3;
85 		uint8_t mode: 2;
86 	} b;
87 	uint8_t w;
88 };
89 
90 union CLICCTRL {
91 	struct {
92 		volatile union CLICINTIP INTIP;
93 		volatile union CLICINTIE INTIE;
94 		volatile union CLICINTATTR INTATTR;
95 		volatile uint8_t INTCTRL;
96 	} w;
97 	uint32_t qw;
98 };
99 
100 /* Nuclei ECLIC register structure */
101 union CLICINFO {
102 	struct {
103 		/** number of max supported interrupts */
104 		uint32_t numint: 13;
105 		/** architecture version */
106 		uint32_t version: 8;
107 		/** supported bits in the clicintctl */
108 		uint32_t intctlbits: 4;
109 		uint32_t _reserved0: 7;
110 	} b;
111 	uint32_t qw;
112 };
113 
114 union CLICMTH {
115 	struct {
116 		uint32_t reserved0: 24;
117 		/**  machine mode interrupt level threshold */
118 		uint32_t mth: 8;
119 	} b;
120 	uint32_t qw;
121 };
122 
123 #endif /*__ASSEMBLER__*/
124 
125 #endif /* ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_CLIC_H_ */
126