1 /* 2 * Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 */ 7 8 #include <zephyr/drivers/pinctrl.h> 9 #include <soc.h> 10 11 #define SAM_PIO_NPINS_PER_BANK 32 12 #define SAM_PIO_BANK(pin_id) (pin_id / SAM_PIO_NPINS_PER_BANK) 13 #define SAM_PIO_LINE(pin_id) (pin_id % SAM_PIO_NPINS_PER_BANK) 14 #define SAM_PIO_BANK_OFFSET 0x40 15 16 #define SAM_GET_PIN_NO(pinmux) ((pinmux) & 0xff) 17 #define SAM_GET_PIN_FUNC(pinmux) ((pinmux >> 16) & 0xf) 18 #define SAM_GET_PIN_IOSET(pinmux) ((pinmux >> 20) & 0xf) 19 20 static pio_registers_t * const pio_reg = 21 (pio_registers_t *)DT_REG_ADDR(DT_NODELABEL(pinctrl)); 22 pinctrl_configure_pin(pinctrl_soc_pin_t pin)23static void pinctrl_configure_pin(pinctrl_soc_pin_t pin) 24 { 25 uint32_t pin_id = SAM_GET_PIN_NO(pin.pin_mux); 26 uint32_t bank = SAM_PIO_BANK(pin_id); 27 uint32_t line = SAM_PIO_LINE(pin_id); 28 uint32_t func = SAM_GET_PIN_FUNC(pin.pin_mux); 29 uint32_t conf = 0; 30 31 pio_reg->PIO_GROUP[bank].PIO_MSKR = 1 << line; 32 33 conf = pio_reg->PIO_GROUP[bank].PIO_CFGR; 34 if (pin.drive_open_drain) { 35 conf |= PIO_CFGR_OPD(PIO_CFGR_OPD_ENABLED_Val); 36 } 37 if (pin.bias_disable) { 38 conf &= ~(PIO_CFGR_PUEN_Msk | PIO_CFGR_PDEN_Msk); 39 } 40 if (pin.bias_pull_down) { 41 conf |= PIO_CFGR_PDEN(PIO_CFGR_PDEN_ENABLED_Val); 42 conf &= ~PIO_CFGR_PUEN_Msk; 43 } 44 if (pin.bias_pull_up) { 45 conf |= PIO_CFGR_PUEN(PIO_CFGR_PUEN_ENABLED_Val); 46 conf &= ~PIO_CFGR_PDEN_Msk; 47 } 48 conf &= ~PIO_CFGR_FUNC_Msk; 49 conf |= PIO_CFGR_FUNC(func); 50 51 pio_reg->PIO_GROUP[bank].PIO_CFGR = conf; 52 } 53 pinctrl_configure_pins(const pinctrl_soc_pin_t * pins,uint8_t pin_cnt,uintptr_t reg)54int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, 55 uintptr_t reg) 56 { 57 ARG_UNUSED(reg); 58 59 for (uint8_t i = 0U; i < pin_cnt; i++) { 60 pinctrl_configure_pin(*pins++); 61 } 62 63 return 0; 64 } 65