1 /*
2 * Copyright (c) 2025 Renesas Electronics Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/device.h>
8 #include <zephyr/spinlock.h>
9 #include <zephyr/drivers/interrupt_controller/gic.h>
10 #include <zephyr/drivers/timer/system_timer.h>
11 #include <zephyr/drivers/clock_control.h>
12 #include <zephyr/irq.h>
13 #include <zephyr/sys_clock.h>
14
15 #define DT_DRV_COMPAT renesas_rza2m_ostm
16
17 DEVICE_MMIO_TOPLEVEL_STATIC(ostm_base, DT_DRV_INST(0));
18
19 /* The interrupt numbers in the device tree are interrupt IDs and need to be converted to SPI
20 * interrupt numbers
21 */
22 #define OSTM_IRQ_NUM (DT_INST_IRQN(0) - GIC_SPI_INT_BASE)
23
24 #if defined(CONFIG_TEST)
25 const int32_t z_sys_timer_irq_for_test = OSTM_IRQ_NUM;
26 #endif
27
28 #define cycle_diff_t uint32_t
29 #define CYCLE_DIFF_MAX (~(cycle_diff_t)0)
30
31 #define OSTM_REG_ADDR(off) ((mm_reg_t)(DEVICE_MMIO_TOPLEVEL_GET(ostm_base) + (off)))
32
33 #define OSTM_CMP_OFFSET 0x0 /* Compare register */
34 #define OSTM_CNT_OFFSET 0x4 /* Counter register */
35
36 #define OSTM_TE_OFFSET 0x10 /* Count enable status register */
37 #define OSTM_TE_ENABLE BIT(0) /* Timer enabled */
38
39 #define OSTM_TS_OFFSET 0x14 /* Count start trigger register */
40 #define OSTM_TS_START BIT(0) /* Trigger start of the timer */
41
42 #define OSTM_TT_OFFSET 0x18 /* Count stop trigger register */
43 #define OSTM_TT_STOP BIT(0) /* Trigger stop of the timer */
44
45 #define OSTM_CTL_OFFSET 0x20 /* Control register */
46 /*
47 * Bit 0 of CTL controls enabling/disabling of OSTMnTINT interrupt requests when counting starts
48 * 0: Disables the interrupts when counting starts
49 * 1: Enables the interrupts when counting starts
50 */
51 #define OSTM_CTL_TRIG_IRQ_ON_START 1
52 /*
53 * Bit 1 of CTL specifies the operating mode for the counter
54 * 0: Interval timer mode
55 * 1: Free-running comparison mode
56 */
57 #define OSTM_CTL_INTERVAL 0
58 #define OSTM_CTL_FREERUN 2
59
60 /*
61 * We have two constraints on the maximum number of cycles we can wait for.
62 *
63 * 1) sys_clock_announce() accepts at most INT32_MAX ticks.
64 *
65 * 2) The number of cycles between two reports must fit in a cycle_diff_t
66 * variable before converting it to ticks.
67 *
68 * Then:
69 *
70 * 3) Pick the smallest between (1) and (2).
71 *
72 * 4) Take into account some room for the unavoidable IRQ servicing latency.
73 * Let's use 3/4 of the max range.
74 *
75 * Finally let's add the LSB value to the result so to clear out a bunch of
76 * consecutive set bits coming from the original max values to produce a
77 * nicer literal for assembly generation.
78 */
79 #define CYCLES_MAX_1 ((uint64_t)INT32_MAX * (uint64_t)CYC_PER_TICK)
80 #define CYCLES_MAX_2 ((uint64_t)CYCLE_DIFF_MAX)
81 #define CYCLES_MAX_3 MIN(CYCLES_MAX_1, CYCLES_MAX_2)
82 #define CYCLES_MAX_4 (CYCLES_MAX_3 / 2 + CYCLES_MAX_3 / 4)
83 #define CYCLES_MAX_5 (CYCLES_MAX_4 + LSB_GET(CYCLES_MAX_4))
84
85 /* Precompute CYCLES_MAX and CYC_PER_TICK at driver init to avoid runtime double divisions */
86 static uint64_t cycles_max;
87 static uint32_t cyc_per_tick;
88 #define CYCLES_MAX cycles_max
89 #define CYC_PER_TICK cyc_per_tick
90
91 static struct k_spinlock lock;
92 static uint64_t last_cycle;
93 static uint64_t last_tick;
94 static uint32_t last_elapsed;
95 extern unsigned int z_clock_hw_cycles_per_sec;
96
ostm_irq_handler(const struct device * dev)97 static void ostm_irq_handler(const struct device *dev)
98 {
99 ARG_UNUSED(dev);
100
101 uint32_t delta_cycles = sys_clock_cycle_get_32() - last_cycle;
102 uint32_t delta_ticks = delta_cycles / CYC_PER_TICK;
103
104 last_cycle += (cycle_diff_t)delta_ticks * CYC_PER_TICK;
105 last_tick += delta_ticks;
106 last_elapsed = 0;
107
108 if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
109 uint32_t next_cycle = last_cycle + CYC_PER_TICK;
110
111 sys_write32(next_cycle, OSTM_REG_ADDR(OSTM_CMP_OFFSET));
112 } else {
113 irq_disable(OSTM_IRQ_NUM);
114 }
115
116 /* Announce to the kernel */
117 sys_clock_announce(delta_ticks);
118 }
119
sys_clock_set_timeout(int32_t ticks,bool idle)120 void sys_clock_set_timeout(int32_t ticks, bool idle)
121 {
122 if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
123 return;
124 }
125
126 if (idle && ticks == K_TICKS_FOREVER) {
127 return;
128 }
129
130 uint32_t next_cycle;
131
132 k_spinlock_key_t key = k_spin_lock(&lock);
133
134 if (ticks == K_TICKS_FOREVER) {
135 next_cycle = last_cycle + CYCLES_MAX;
136 } else {
137 next_cycle = (last_tick + last_elapsed + ticks) * CYC_PER_TICK;
138 if ((next_cycle - last_cycle) > CYCLES_MAX) {
139 next_cycle = last_cycle + CYCLES_MAX;
140 }
141 }
142
143 sys_write32(next_cycle, OSTM_REG_ADDR(OSTM_CMP_OFFSET));
144 irq_enable(OSTM_IRQ_NUM);
145
146 k_spin_unlock(&lock, key);
147 }
148
sys_clock_elapsed(void)149 uint32_t sys_clock_elapsed(void)
150 {
151 if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
152 return 0;
153 }
154
155 uint32_t delta_cycles = sys_clock_cycle_get_32() - last_cycle;
156 uint32_t delta_ticks = delta_cycles / CYC_PER_TICK;
157
158 last_elapsed = delta_ticks;
159
160 return delta_ticks;
161 }
162
sys_clock_disable(void)163 void sys_clock_disable(void)
164 {
165 if ((sys_read8(OSTM_REG_ADDR(OSTM_TE_OFFSET)) & OSTM_TE_ENABLE) != OSTM_TE_ENABLE) {
166 return;
167 }
168
169 sys_write8(OSTM_TT_STOP, OSTM_REG_ADDR(OSTM_TT_OFFSET));
170 while ((sys_read8(OSTM_REG_ADDR(OSTM_TE_OFFSET)) & OSTM_TE_ENABLE) == OSTM_TE_ENABLE) {
171 ;
172 }
173 }
174
sys_clock_cycle_get_32(void)175 uint32_t sys_clock_cycle_get_32(void)
176 {
177 k_spinlock_key_t key = k_spin_lock(&lock);
178 uint32_t ostm_cnt = sys_read32(OSTM_REG_ADDR(OSTM_CNT_OFFSET));
179
180 k_spin_unlock(&lock, key);
181
182 return ostm_cnt;
183 }
184
sys_clock_driver_init(void)185 static int sys_clock_driver_init(void)
186 {
187 int ret;
188 const struct device *clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0));
189 uint32_t clock_subsys = DT_INST_CLOCKS_CELL(0, clk_id);
190
191 if (!device_is_ready(clock_dev)) {
192 return -ENODEV;
193 }
194
195 ret = clock_control_on(clock_dev, (clock_control_subsys_t)&clock_subsys);
196
197 if (ret < 0) {
198 return ret;
199 }
200
201 ret = clock_control_get_rate(clock_dev, (clock_control_subsys_t)&clock_subsys,
202 &z_clock_hw_cycles_per_sec);
203 if (ret < 0) {
204 return ret;
205 }
206
207 last_tick = 0;
208 last_cycle = 0;
209 cyc_per_tick = sys_clock_hw_cycles_per_sec() / CONFIG_SYS_CLOCK_TICKS_PER_SEC;
210 cycles_max = CYCLES_MAX_5;
211
212 DEVICE_MMIO_TOPLEVEL_MAP(ostm_base, K_MEM_CACHE_NONE);
213
214 IRQ_CONNECT(OSTM_IRQ_NUM, DT_INST_IRQ(0, priority), ostm_irq_handler, NULL,
215 DT_INST_IRQ(0, flags));
216
217 /* Restarting the timer will cause reset of CNT register in free-running mode */
218 sys_clock_disable();
219
220 sys_write32(cyc_per_tick, OSTM_REG_ADDR(OSTM_CMP_OFFSET));
221 sys_write8(OSTM_CTL_FREERUN, OSTM_REG_ADDR(OSTM_CTL_OFFSET));
222 sys_write8(OSTM_TS_START, OSTM_REG_ADDR(OSTM_TS_OFFSET));
223
224 irq_enable(OSTM_IRQ_NUM);
225 return 0;
226 }
227 SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2, CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
228