1 /* 2 * Copyright (c) 2025 Antmicro <www.antmicro.com> 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_VIRTIO_VIRTIO_COMMON_H_ 8 #define ZEPHYR_VIRTIO_VIRTIO_COMMON_H_ 9 10 #define DEVICE_STATUS_ACKNOWLEDGE 0 11 #define DEVICE_STATUS_DRIVER 1 12 #define DEVICE_STATUS_DRIVER_OK 2 13 #define DEVICE_STATUS_FEATURES_OK 3 14 #define DEVICE_STATUS_NEEDS_RESET 6 15 #define DEVICE_STATUS_FAILED 7 16 17 #define VIRTIO_F_VERSION_1 32 18 19 /* Ranges of feature bits for specific device types (see spec 2.2)*/ 20 #define DEV_TYPE_FEAT_RANGE_0_BEGIN 0 21 #define DEV_TYPE_FEAT_RANGE_0_END 23 22 #define DEV_TYPE_FEAT_RANGE_1_BEGIN 50 23 #define DEV_TYPE_FEAT_RANGE_1_END 127 24 25 /* 26 * While defined separately in 4.1.4.5 for PCI and in 4.2.2 for MMIO 27 * the same bits are responsible for the same interrupts, so defines 28 * with them can be unified 29 */ 30 #define VIRTIO_QUEUE_INTERRUPT 1 31 #define VIRTIO_DEVICE_CONFIGURATION_INTERRUPT 2 32 33 /* 34 * VIRTIO-MMIO register definitions. 35 * 36 * Based on Virtual I/O Device (VIRTIO) Version 1.3 specification: 37 * https://docs.oasis-open.org/virtio/virtio/v1.3/csd01/virtio-v1.3-csd01.pdf 38 */ 39 40 #define VIRTIO_MMIO_MAGIC_VALUE 0x000 41 #define VIRTIO_MMIO_VERSION 0x004 42 #define VIRTIO_MMIO_DEVICE_ID 0x008 43 #define VIRTIO_MMIO_VENDOR_ID 0x00c 44 #define VIRTIO_MMIO_DEVICE_FEATURES 0x010 45 #define VIRTIO_MMIO_DEVICE_FEATURES_SEL 0x014 46 #define VIRTIO_MMIO_DRIVER_FEATURES 0x020 47 #define VIRTIO_MMIO_DRIVER_FEATURES_SEL 0x024 48 #define VIRTIO_MMIO_QUEUE_SEL 0x030 49 #define VIRTIO_MMIO_QUEUE_SIZE_MAX 0x034 50 #define VIRTIO_MMIO_QUEUE_SIZE 0x038 51 #define VIRTIO_MMIO_QUEUE_READY 0x044 52 #define VIRTIO_MMIO_QUEUE_NOTIFY 0x050 53 #define VIRTIO_MMIO_INTERRUPT_STATUS 0x060 54 #define VIRTIO_MMIO_INTERRUPT_ACK 0x064 55 #define VIRTIO_MMIO_STATUS 0x070 56 #define VIRTIO_MMIO_QUEUE_DESC_LOW 0x080 57 #define VIRTIO_MMIO_QUEUE_DESC_HIGH 0x084 58 #define VIRTIO_MMIO_QUEUE_AVAIL_LOW 0x090 59 #define VIRTIO_MMIO_QUEUE_AVAIL_HIGH 0x094 60 #define VIRTIO_MMIO_QUEUE_USED_LOW 0x0a0 61 #define VIRTIO_MMIO_QUEUE_USED_HIGH 0x0a4 62 #define VIRTIO_MMIO_SHM_SEL 0x0ac 63 #define VIRTIO_MMIO_SHM_LEN_LOW 0x0b0 64 #define VIRTIO_MMIO_SHM_LEN_HIGH 0x0b4 65 #define VIRTIO_MMIO_SHM_BASE_LOW 0x0b8 66 #define VIRTIO_MMIO_SHM_BASE_HIGH 0x0bc 67 #define VIRTIO_MMIO_QUEUE_RESET 0x0c0 68 #define VIRTIO_MMIO_CONFIG_GENERATION 0x0fc 69 #define VIRTIO_MMIO_CONFIG 0x100 70 71 /** 72 * Common virtio isr 73 * 74 * @param dev virtio device it operates on 75 * @param isr_status value of isr status register 76 * @param virtqueue_count amount of available virtqueues 77 */ 78 void virtio_isr(const struct device *dev, uint8_t isr_status, uint16_t virtqueue_count); 79 80 #endif /*ZEPHYR_VIRTIO_VIRTIO_COMMON_H_*/ 81