1# Copyright (c) 2020 Hubert Miś <hubert.mis@gmail.com>
2# SPDX-License-Identifier: Apache-2.0
3
4title: FTDI FT800 graphic controller
5
6description: |
7    The FTDI FT800 graphic controller is a graphics accelerator,
8    able to drive LCD displays with RGB parallel output.
9    It communicates with MCU through SPI commands.
10    It also includes touchscreen and sound output support.
11
12compatible: "ftdi,ft800"
13
14include: spi-device.yaml
15
16properties:
17  irq-gpios:
18    type: phandle-array
19    description: Optional IRQ line of FT800 controller
20
21  pclk:
22    type: int
23    required: true
24    description: |
25      The value to divide the main clock by for PCLK. If the
26      typical main clock was 48MHz and this value is 5, the PCLK
27      will be 9.6 MHz. Must be positive value to enable the screen
28
29  pclk-pol:
30    type: int
31    required: true
32    description: |
33      Polarity of PCLK. If it is set to zero, PCLK polarity is on
34      the rising edge. If it is set to one, PCLK polarity is on
35      the falling edge.
36
37  cspread:
38    type: int
39    required: true
40    description: |
41      Controls the transition of RGB signals with PCLK active clock
42      edge. When set to 0, R[7:2],G[7:2] and B[7:2] signals change
43      following the active edge of PCLK. When set to 1, R[7:2]
44      changes a PCLK clock early and B[7:2] a PCLK clock later,
45      which helps reduce the system noise.
46
47  swizzle:
48    type: int
49    required: true
50    description: |
51      Controls the arrangement of output RGB pins, which may help
52      support different LCD panel. Please check FT800 Programmers
53      Guide for details.
54
55  vsize:
56    type: int
57    required: true
58    description: Number of visible lines of pixels in one frame
59
60  voffset:
61    type: int
62    required: true
63    description: Number of invisible lines at the beginning of a new frame
64
65  vcycle:
66    type: int
67    required: true
68    description: |
69      Number of all lines in a frame. It includes all visible and
70      invisible lines at the beginning and at the end of a frame.
71
72  vsync0:
73    type: int
74    required: true
75    description: |
76      Number of lines for the high state of signal VSYNC at
77      the start of new frame.
78
79  vsync1:
80    type: int
81    required: true
82    description: |
83      Number of lines for signal VSYNC toggle takes at the start
84      of new frame.
85
86  hsize:
87    type: int
88    required: true
89    description: Number of PCLK cycles per visible part of horizontal line
90
91  hoffset:
92    type: int
93    required: true
94    description: |
95      Number of PCLK cycles before pixels are scanned out for
96      given line
97
98  hcycle:
99    type: int
100    required: true
101    description: Number of total PCLK cycles per horizontal line scan.
102
103  hsync0:
104    type: int
105    required: true
106    description: Number of PCLK cycles of HSYNC high state during start of
107      line
108
109  hsync1:
110    type: int
111    required: true
112    description: Number of PCLK cycles for HSYNC toggle during start of line.
113