1# Copyright (c) 2025 Analog Devices, Inc.
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  MAX32 HyperBus (HPB) Memory Controller Interface
6
7  The HyperBus and Xccela Memory Controller interface is a high-speed, low-pin
8  count interface for connecting to one or more compatible external memory
9  devices. The external HyperBus or Xccela Bus memory device is mapped into the
10  memory space enabling direct code execution, data storage, or both.
11
12  The memory devices are defined as children of the HPB memory controller node.
13
14  &hpb {
15      status = "okay";
16      pinctrl-0 = <&hyp_cs0n_p1_11 &hyp_d0_p1_12 &hyp_d1_p1_15
17                   &hyp_d2_p1_19 &hyp_d3_p1_20 &hyp_d4_p1_13
18                   &hyp_d5_p1_16 &hyp_d6_p1_18 &hyp_d7_p1_21>;
19      pinctrl-names = "default";
20
21      mem@0 {
22          reg = <0>;
23          base-address = <0x60000000>;
24          device-type = <ADI_MAX32_HPB_DEV_TYPE_HYPER_RAM>;
25          config-regs =     <1>;
26          config-reg-vals = <2>;
27      };
28  };
29
30  Note: the values for most properties take values from
31  zephyr/dt-bindings/memory-controller/adi-max32-hpb.h header which will need to
32  be included.
33
34  Finally, in order to make the memory available you will need to define new
35  memory device/s in DeviceTree, e.g.:
36
37  sdram1: sdram@60000000 {
38      compatible = "zephyr,memory-region", "mmio-sram";
39      device_type = "memory";
40      reg = <0x60000000 DT_SIZE_M(X)>;
41      zephyr,memory-region = "SDRAM1";
42  };
43
44compatible: "adi,max32-hpb"
45
46include: [base.yaml, pinctrl-device.yaml]
47
48properties:
49  reg:
50    required: true
51
52  clocks:
53    required: true
54
55  pinctrl-0:
56    required: true
57
58  pinctrl-names:
59    required: true
60
61  "#address-cells":
62    required: true
63    const: 1
64
65  "#size-cells":
66    required: true
67    const: 0
68
69  enable-emcc:
70    type: boolean
71    description: |
72      Enable the EMCC cache controller for the HyperBus memory devices.
73
74child-binding:
75  description: Memory device.
76
77  properties:
78    reg:
79      type: int
80      required: true
81
82    base-address:
83      type: int
84      description: |
85        The address to which to map this memory device, e.g. 0x60000000. See the
86        user guide for your specific SoC for the allowed range for mapping.
87
88    device-type:
89      type: int
90      required: true
91      description: |
92        The type of attached memory device, i.e. Hyper Flash, Xccela PSRAM, or
93        Hyper RAM.
94
95    fixed-read-latency:
96      type: boolean
97      description: |
98        Enable Xccela bus Fixed Read Latency. Should match the Latency Type
99        configuration in the target PSRAM.
100
101    read-cs-high:
102      type: int
103      description: |
104        The CS# high time, in clock cycles, between read operations.
105
106    write-cs-high:
107      type: int
108      description: |
109        The CS# high time, in clock cycles, between write operations.
110
111    read-cs-setup:
112      type: int
113      description: |
114        The CS# latency, in clock cycles, for read operations. This adds
115        additional clock cycles after CS# goes low.
116
117    write-cs-setup:
118      type: int
119      description: |
120        The CS# latency, in clock cycles, for write operations. This adds
121        additional clock cycles after CS# goes low.
122
123    read-cs-hold:
124      type: int
125      description: |
126        The CS# hold time, in clock cycles, between the completion of a read
127        operation and the CS# deassertion.
128
129    write-cs-hold:
130      type: int
131      description: |
132        The CS# hold time, in clock cycles, between the completion of a write
133        operation and the CS# deassertion.
134
135    latency-cycles:
136      type: int
137      description: |
138        For HyperRAM: set this property to match the external HyperRAM Read
139        Latency Configuration Register value.
140
141        For Xccela PSRAM: The value is adjusted based on `fixed-read-latency`
142        property also being set.
143
144    config-regs:
145      type: array
146      description: |
147        Configuration register addresses to set on the memory device during
148        initialization.
149
150    config-reg-vals:
151      type: array
152      description: |
153        Configuration register values to set on the memory device during
154        initialization.
155