1# Copyright (c) 2020, Teslabs Engineering S.L.
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  STM32 Flexible Memory Controller (SDRAM controller).
6
7  The FMC SDRAM controller can be used to interface with external SDRAM
8  memories. Up to 2 SDRAM banks are supported with independent configuration. It
9  is worth to note that while settings are independent, some are shared or are
10  required to be set according to the most constraining device. Refer to the
11  properties description or the datasheet for more details.
12
13  The FMC SDRAM controller is defined below the FMC node and SDRAM banks are
14  defined as child nodes of the FMC SDRAM node. You can either have bank 1 (@0),
15  bank 2 (@1) or both. You can enable the FMC SDRAM controller in your board
16  DeviceTree file like this:
17
18  &fmc {
19      status = "okay";
20      pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1 &fmc_nbl2_pi4...>;
21
22      sdram {
23          status = "okay";
24
25          power-up-delay = <100>;
26          num-auto-refresh = <8>;
27          mode-register = <0x220>;
28          refresh-rate = <603>;
29
30          bank@0 {
31              reg = <0>;
32
33              st,sdram-control = <STM32_FMC_SDRAM_NC_9
34                                  STM32_FMC_SDRAM_NR_12
35                                  STM32_FMC_SDRAM_MWID_32
36                                  STM32_FMC_SDRAM_NB_4
37                                  STM32_FMC_SDRAM_CAS_2
38                                  STM32_FMC_SDRAM_SDCLK_PERIOD_2
39                                  STM32_FMC_SDRAM_RBURST_ENABLE
40                                  STM32_FMC_SDRAM_RPIPE_0>;
41              st,sdram-timing = <2 6 4 6 2 2 2>;
42          };
43
44          bank@1 {
45              reg = <1>;
46              ...
47          };
48      };
49  };
50
51  Note that you will find definitions for the st,sdram-control field at
52  dt-bindings/memory-controller/stm32-fmc-sdram.h. This file is already included
53  in the SoC DeviceTree files.
54
55  Finally, in order to make the memory available you will need to define new
56  memory device/s in DeviceTree:
57
58  sdram1: sdram@c0000000 {
59      compatible = "zephyr,memory-region", "mmio-sram";
60      device_type = "memory";
61      reg = <0xc0000000 DT_SIZE_M(X)>;
62      zephyr,memory-region = "SDRAM1";
63  };
64
65  sdram2: sdram@d0000000 {
66      compatible = "zephyr,memory-region", "mmio-sram";
67      device_type = "memory";
68      reg = <0xd0000000 DT_SIZE_M(X)>;
69      zephyr,memory-region = "SDRAM2";
70  };
71
72  It is important to use sdram1 and sdram2 node labels for bank 1 and bank 2
73  respectively. Memory addresses are 0xc0000000 and 0xd0000000 for bank 1 and
74  bank 2 respectively.
75
76compatible: "st,stm32-fmc-sdram"
77
78include: base.yaml
79
80properties:
81  "#address-cells":
82    required: true
83    const: 1
84
85  "#size-cells":
86    required: true
87    const: 0
88
89  power-up-delay:
90    type: int
91    default: 100
92    description: Power-up delay in microseconds.
93
94  num-auto-refresh:
95    type: int
96    default: 8
97    description: Number of auto-refresh commands issued.
98
99  mode-register:
100    type: int
101    required: true
102    description:
103      A 14-bit field that defines the SDRAM Mode Register content. The mode
104      register bits are also used to program the extended mode register for
105      mobile SDRAM.
106
107  refresh-rate:
108    type: int
109    required: true
110    description:
111      A 13-bit field defines the refresh rate of the SDRAM device. It is
112      expressed in number of memory clock cycles. It must be set at least to
113      41 SDRAM clock cycles.
114
115child-binding:
116  description: SDRAM bank.
117
118  properties:
119    reg:
120      type: int
121      required: true
122
123    st,sdram-control:
124      type: array
125      required: true
126      description: |
127        SDRAM control configuration. Expected fields, in order, are,
128
129        - NC: Number of bits of a column address.
130        - NR: Number of bits of a row address.
131        - MWID: Memory device width.
132        - NB: Number of internal banks.
133        - CAS: SDRAM CAS latency in number of memory clock cycles.
134        - SDCLK: SDRAM clock period. If two SDRAM devices are used both should
135          have the same value.
136        - RBURST: Enable burst read mode. If two SDRAM devices are used both
137          should have the same value.
138        - RPIPE: Delay, in fmc_ker_ck clock cycles, for reading data after CAS
139          latency. If two SDRAM devices are used both should have the same
140          value.
141
142    st,sdram-timing:
143      type: array
144      required: true
145      description: |
146        SDRAM timing configuration. Expected fields, in order, are,
147
148        - TMRD: Delay between a Load Mode Register command and an Active or
149          Refresh command in number of memory clock cycles.
150        - TXSR: Delay from releasing the Self-refresh command to issuing the
151          Activate command in number of memory clock cycles. If two SDRAM
152          devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with
153          the same TXSR timing corresponding to the slowest SDRAM device
154        - TRAS: Minimum Self-refresh period in number of memory clock cycles.
155        - TRC: Delay between the Refresh command and the Activate command, as
156          well as the delay between two consecutive Refresh commands. It is
157          expressed in number of memory clock cycles. If two SDRAM devices are
158          used, the TRC must be programmed with the timings of the slowest
159          device in both banks.
160        - TWP: Delay between a Write and a Precharge command in number of memory
161          clock cycles
162        - TRP: Delay between a Precharge command and another command in number
163          of memory clock cycles. If two SDRAM devices are used, the TRP must be
164          programmed with the timing of the slowest device in both banks.
165        - TRCD: Delay between the Activate command and a Read/Write command in
166          number of memory clock cycles.
167