1# Copyright (c) 2025 Microchip Technology Inc. 2# SPDX-License-Identifier: Apache-2.0 3 4title: Microchip SERCOM UART controller 5 6description: | 7 Microchip SERCOM UART driver. 8 9 Group g1 SERCOM UART driver supports following hardware peripherals: 10 - module name="SERCOM" id="U2201" version="5.0.0" 11 12compatible: "microchip,sercom-g1-uart" 13 14include: 15 - name: uart-controller.yaml 16 - name: pinctrl-device.yaml 17 18properties: 19 reg: 20 required: true 21 22 interrupts: 23 required: true 24 25 clocks: 26 required: true 27 28 clock-names: 29 required: true 30 31 rxpo: 32 type: int 33 required: true 34 description: | 35 Define the receive data (RxD) pin configuration. 36 An enumeration with the following values: 37 38 +-------+---------------+ 39 | Value | RX Pin | 40 +-------+---------------+ 41 | 0 | SERCOM_PAD[0] | 42 +-------+---------------+ 43 | 1 | SERCOM_PAD[1] | 44 +-------+---------------+ 45 | 2 | SERCOM_PAD[2] | 46 +-------+---------------+ 47 | 3 | SERCOM_PAD[3] | 48 +-------+---------------+ 49 50 txpo: 51 type: int 52 required: true 53 description: | 54 Transmit Data Pinout. An enumeration with values that depend on the 55 hardware being used. This controls both the transmit pins and if 56 hardware flow control is used. 57 58 SAMD5/E5: 59 60 +-------+---------------+---------------+---------------+ 61 | Value | TX Pin | RTS | CTS | 62 +-------+---------------+---------------+---------------+ 63 | 0 | SERCOM_PAD[0] | N/A | N/A | 64 +-------+---------------+---------------+---------------+ 65 | 1 | Reserved | 66 +-------+---------------+---------------+---------------+ 67 | 2 | SERCOM_PAD[0] | SERCOM_PAD[2] | SERCOM_PAD[3] | 68 +-------+---------------+---------------+---------------+ 69 | 3 | SERCOM_PAD[0] | SERCOM_PAD[2] | N/A | 70 +-------+---------------+---------------+---------------+ 71 72 clock-external: 73 type: boolean 74 description: | 75 select external clock for uart (external clock if true). 76 77 collision-detection: 78 type: boolean 79 description: | 80 Enable collision detection for half-duplex mode. 81