1 /*
2  * Copyright (c) 2017 Nordic Semiconductor ASA
3  * Copyright 2023,2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
4  *
5  * SPDX-License-Identifier: Apache-2.0
6  */
7 
8 /**
9  * @file
10  * @brief CMSIS interface file
11  *
12  * This header populates the default values required to configure the
13  * ARM CMSIS Core headers.
14  */
15 
16 #ifndef ZEPHYR_MODULES_CMSIS_6_CMSIS_CORE_M_DEFAULTS_H_
17 #define ZEPHYR_MODULES_CMSIS_6_CMSIS_CORE_M_DEFAULTS_H_
18 
19 #include <zephyr/arch/arm/cortex_m/nvic.h>
20 
21 #ifdef __cplusplus
22 extern "C" {
23 #endif
24 
25 /* Fill in CMSIS required values for non-CMSIS compliant SoCs.
26  * Use __NVIC_PRIO_BITS as it is required and simple to check, but
27  * ultimately all SoCs will define their own CMSIS types and constants.
28  */
29 #ifndef __NVIC_PRIO_BITS
30 typedef enum {
31 	Reset_IRQn                    = -15,
32 	NonMaskableInt_IRQn           = -14,
33 	HardFault_IRQn                = -13,
34 #if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
35 	MemoryManagement_IRQn         = -12,
36 	BusFault_IRQn                 = -11,
37 	UsageFault_IRQn               = -10,
38 #if defined(CONFIG_ARM_SECURE_FIRMWARE)
39 	SecureFault_IRQn              = -9,
40 #endif /* CONFIG_ARM_SECURE_FIRMWARE */
41 #endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
42 	SVCall_IRQn                   =  -5,
43 	DebugMonitor_IRQn             =  -4,
44 	PendSV_IRQn                   =  -2,
45 	SysTick_IRQn                  =  -1,
46 	Max_IRQn                      =  CONFIG_NUM_IRQS,
47 } IRQn_Type;
48 
49 #if defined(CONFIG_CPU_CORTEX_M0)
50 #define __CM0_REV        0
51 #elif defined(CONFIG_CPU_CORTEX_M0PLUS)
52 #define __CM0PLUS_REV    0
53 #elif defined(CONFIG_CPU_CORTEX_M1)
54 #define __CM1_REV        0
55 #elif defined(CONFIG_CPU_CORTEX_M3)
56 #define __CM3_REV        0
57 #elif defined(CONFIG_CPU_CORTEX_M4)
58 #define __CM4_REV        0
59 #elif defined(CONFIG_CPU_CORTEX_M7)
60 #define __CM7_REV        0
61 #elif defined(CONFIG_CPU_CORTEX_M23)
62 #define __CM23_REV       0
63 #elif defined(CONFIG_CPU_CORTEX_M33)
64 #define __CM33_REV       0
65 #elif defined(CONFIG_CPU_CORTEX_M52)
66 #define __CM52_REV       0
67 #elif defined(CONFIG_CPU_CORTEX_M55)
68 #define __CM55_REV       0
69 #elif defined(CONFIG_CPU_CORTEX_M85)
70 #define __CM85_REV       0
71 #else
72 #error "Unknown Cortex-M device"
73 #endif
74 
75 #define __NVIC_PRIO_BITS               NUM_IRQ_PRIO_BITS
76 #define __Vendor_SysTickConfig         0 /* Default to standard SysTick */
77 #endif /* __NVIC_PRIO_BITS */
78 
79 #ifndef __MPU_PRESENT
80 #define __MPU_PRESENT             CONFIG_CPU_HAS_ARM_MPU
81 #endif
82 
83 #ifndef __FPU_PRESENT
84 #define __FPU_PRESENT             CONFIG_CPU_HAS_FPU
85 #endif
86 
87 #ifndef __FPU_DP
88 #define __FPU_DP                  CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION
89 #endif
90 
91 #ifndef __VTOR_PRESENT
92 #define __VTOR_PRESENT            CONFIG_CPU_CORTEX_M_HAS_VTOR
93 #endif
94 
95 #ifndef __DSP_PRESENT
96 #define __DSP_PRESENT             CONFIG_ARMV8_M_DSP
97 #endif
98 
99 #ifndef __ICACHE_PRESENT
100 #define __ICACHE_PRESENT          CONFIG_CPU_HAS_ICACHE
101 #endif
102 
103 #ifndef __DCACHE_PRESENT
104 #define __DCACHE_PRESENT          CONFIG_CPU_HAS_DCACHE
105 #endif
106 
107 #ifndef __MVE_PRESENT
108 #define __MVE_PRESENT             CONFIG_ARMV8_1_M_MVEI
109 #endif
110 
111 #ifndef __SAUREGION_PRESENT
112 #define __SAUREGION_PRESENT       CONFIG_CPU_HAS_ARM_SAU
113 #endif
114 
115 #ifndef __PMU_PRESENT
116 #define __PMU_PRESENT             CONFIG_ARMV8_1_M_PMU
117 #define __PMU_NUM_EVENTCNT        CONFIG_ARMV8_1_M_PMU_EVENTCNT
118 #endif
119 
120 #ifdef __cplusplus
121 }
122 #endif
123 
124 #if defined(CONFIG_CPU_CORTEX_M0)
125 #include <core_cm0.h>
126 #elif defined(CONFIG_CPU_CORTEX_M0PLUS)
127 #include <core_cm0plus.h>
128 #elif defined(CONFIG_CPU_CORTEX_M1)
129 #include <core_cm1.h>
130 #elif defined(CONFIG_CPU_CORTEX_M3)
131 #include <core_cm3.h>
132 #elif defined(CONFIG_CPU_CORTEX_M4)
133 #include <core_cm4.h>
134 #elif defined(CONFIG_CPU_CORTEX_M7)
135 #include <core_cm7.h>
136 #elif defined(CONFIG_CPU_CORTEX_M23)
137 #include <core_cm23.h>
138 #elif defined(CONFIG_CPU_CORTEX_M33)
139 #include <core_cm33.h>
140 #elif defined(CONFIG_CPU_CORTEX_M52)
141 #include <core_cm52.h>
142 #elif defined(CONFIG_CPU_CORTEX_M55)
143 #include <core_cm55.h>
144 #elif defined(CONFIG_CPU_CORTEX_M85)
145 #include <core_cm85.h>
146 #else
147 #error "Unknown Cortex-M device"
148 #endif
149 
150 #endif /* ZEPHYR_MODULES_CMSIS_6_CMSIS_CORE_M_DEFAULTS_H_ */
151