1/*
2 * Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/**
8 * @file
9 * @brief Linker command/script file
10 *
11 * Linker script for the Cortex-M platforms.
12 */
13
14#include <zephyr/linker/sections.h>
15#include <zephyr/devicetree.h>
16
17#include <zephyr/linker/linker-defs.h>
18#include <zephyr/linker/linker-tool.h>
19
20#if defined(CONFIG_NORDIC_QSPI_NOR) && defined(CONFIG_SOC_NRF5340_CPUAPP)
21
22/* On nRF5340, external flash is mapped in XIP region at 0x1000_0000. */
23
24#define EXTFLASH_NODE	DT_INST(0, nordic_qspi_nor)
25#define EXTFLASH_ADDR	0x10000000
26#define EXTFLASH_SIZE	DT_PROP_OR(EXTFLASH_NODE, size_in_bytes, \
27				   DT_PROP(EXTFLASH_NODE, size) / 8)
28
29#elif defined(CONFIG_FLASH_ADI_MAX32_SPIXF) && DT_NODE_EXISTS(DT_INST(0, adi_max32_spixf_nor))
30
31/* On MAX32 SPIXF, external flash is mapped in XIP region at 0x8000_0000. */
32
33#define EXTFLASH_NODE	DT_INST(0, adi_max32_spixf_nor)
34#define EXTFLASH_ADDR	DT_REG_ADDR(DT_INST(0, adi_max32_spixf_nor))
35#define EXTFLASH_SIZE	DT_REG_SIZE(DT_INST(0, adi_max32_spixf_nor))
36
37#elif defined(CONFIG_STM32_MEMMAP) && DT_NODE_EXISTS(DT_INST(0, st_stm32_ospi_nor))
38/* On stm32 OSPI, external flash is mapped in XIP region at address given by the reg property. */
39
40#define EXTFLASH_NODE	DT_INST(0, st_stm32_ospi_nor)
41#define EXTFLASH_ADDR	DT_REG_ADDR_BY_IDX(DT_PARENT(EXTFLASH_NODE), 1)
42#define EXTFLASH_SIZE	(DT_PROP(EXTFLASH_NODE, size) / 8)
43
44#elif defined(CONFIG_STM32_MEMMAP) && DT_NODE_EXISTS(DT_INST(0, st_stm32_qspi_nor))
45/* On stm32 QSPI, external flash is mapped in XIP region at address given by the reg property. */
46
47#define EXTFLASH_NODE	DT_INST(0, st_stm32_qspi_nor)
48#define EXTFLASH_ADDR	DT_REG_ADDR_BY_IDX(DT_PARENT(EXTFLASH_NODE), 1)
49#define EXTFLASH_SIZE	(DT_PROP(EXTFLASH_NODE, size) / 8)
50
51#elif defined(CONFIG_STM32_MEMMAP) && DT_NODE_EXISTS(DT_INST(0, st_stm32_xspi_nor))
52/* On stm32 XSPI, external flash is mapped in XIP region at address given by the reg property. */
53
54#define EXTFLASH_NODE	DT_INST(0, st_stm32_xspi_nor)
55#define EXTFLASH_ADDR	DT_REG_ADDR_BY_IDX(DT_PARENT(EXTFLASH_NODE), 1)
56#define EXTFLASH_SIZE	(DT_PROP(EXTFLASH_NODE, size) / 8)
57
58#elif defined(CONFIG_FLASH_MSPI_NOR) && defined(CONFIG_SOC_NRF54H20_CPUAPP)
59
60#define EXTFLASH_NODE	DT_INST(0, jedec_mspi_nor)
61#define EXTFLASH_ADDR	0x60000000
62#define EXTFLASH_SIZE	DT_PROP_OR(EXTFLASH_NODE, size_in_bytes, \
63				   DT_PROP(EXTFLASH_NODE, size) / 8)
64
65#else
66
67/*
68 * Add another fake portion of FLASH to simulate a secondary or external FLASH
69 * that we can do XIP from.
70 */
71#define EXTFLASH_ADDR	0x7000
72#define EXTFLASH_SIZE	(CONFIG_FLASH_SIZE * 1K - EXTFLASH_ADDR)
73
74#endif
75
76MEMORY
77{
78	EXTFLASH (rx) : ORIGIN = EXTFLASH_ADDR, LENGTH = EXTFLASH_SIZE
79}
80
81#include <zephyr/arch/arm/cortex_m/scripts/linker.ld>
82