1 /*
2 * Copyright (c) 2020 Antmicro <www.antmicro.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6 #include <zephyr/kernel.h>
7 #include <stdio.h>
8 #include <zephyr/devicetree.h>
9 #include <zephyr/drivers/clock_control.h>
10 #include <zephyr/drivers/clock_control/clock_control_litex.h>
11 /* Test defines */
12
13 /* Select clock outputs for tests [0-6] */
14 #define LITEX_CLK_TEST_CLK1 0
15 #define LITEX_CLK_TEST_CLK2 1
16
17 /* Values for frequency test */
18 #define LITEX_TEST_FREQUENCY_DUTY_VAL 50 /* [%] */
19 #define LITEX_TEST_FREQUENCY_PHASE_VAL 0 /* [deg] */
20 #define LITEX_TEST_FREQUENCY_DELAY_MS 1000 /* [ms] */
21 #define LITEX_TEST_FREQUENCY_MIN 5000000 /* [Hz] */
22 #define LITEX_TEST_FREQUENCY_MAX 1200000000 /* [Hz] */
23 #define LITEX_TEST_FREQUENCY_STEP 1000000 /* [Hz] */
24
25 /* Values for duty test */
26 #define LITEX_TEST_DUTY_FREQ_VAL 20000000 /* [Hz] */
27 #define LITEX_TEST_DUTY_PHASE_VAL 0 /* [deg] */
28 #define LITEX_TEST_DUTY_DELAY_MS 250 /* [ms] */
29 #define LITEX_TEST_DUTY_MIN 0 /* [%] */
30 #define LITEX_TEST_DUTY_MAX 100 /* [%] */
31 #define LITEX_TEST_DUTY_STEP 1 /* [%] */
32
33 /* Values for phase test */
34 #define LITEX_TEST_PHASE_FREQ_VAL 25000000 /* [Hz] */
35 #define LITEX_TEST_PHASE_DUTY_VAL 50 /* [%] */
36 #define LITEX_TEST_PHASE_DELAY_MS 50 /* [ms] */
37 #define LITEX_TEST_PHASE_MIN 0 /* [deg] */
38 #define LITEX_TEST_PHASE_MAX 360 /* [deg] */
39 #define LITEX_TEST_PHASE_STEP 1 /* [deg] */
40
41 /* Values for single parameters test */
42 #define LITEX_TEST_SINGLE_FREQ_VAL 15000000 /* [Hz] */
43 #define LITEX_TEST_SINGLE_DUTY_VAL 25 /* [%] */
44 #define LITEX_TEST_SINGLE_PHASE_VAL 90 /* [deg] */
45 #define LITEX_TEST_SINGLE_FREQ_VAL2 15000000 /* [Hz] */
46 #define LITEX_TEST_SINGLE_DUTY_VAL2 75 /* [%] */
47 #define LITEX_TEST_SINGLE_PHASE_VAL2 0 /* [deg] */
48
49 /* loop tests infinitely if true, otherwise do one loop */
50 #define LITEX_TEST_LOOP 0
51
52 /* Choose test type */
53 #define LITEX_TEST 4
54
55 #define LITEX_TEST_FREQUENCY 1
56 #define LITEX_TEST_DUTY 2
57 #define LITEX_TEST_PHASE 3
58 #define LITEX_TEST_SINGLE 4
59
60 #define LITEX_TEST_DUTY_DEN 100
61
62 /* LiteX Common Clock Driver tests */
litex_clk_test_getters(const struct device * dev)63 int litex_clk_test_getters(const struct device *dev)
64 {
65 struct litex_clk_setup setup;
66 uint32_t rate;
67 int i;
68
69 clock_control_subsys_t sub_system = (clock_control_subsys_t)&setup;
70
71 printf("Getters test\n");
72 for (i = 0; i < NCLKOUT; i++) {
73 setup.clkout_nr = i;
74 clock_control_get_status(dev, sub_system);
75 printf("CLKOUT%d: get_status: rate:%d phase:%d duty:%d\n",
76 i, setup.rate, setup.phase, setup.duty);
77 clock_control_get_rate(dev, sub_system, &rate);
78 printf("CLKOUT%d: get_rate:%d\n", i, rate);
79 }
80
81 return 0;
82 }
83
litex_clk_test_single(const struct device * dev)84 int litex_clk_test_single(const struct device *dev)
85 {
86 struct litex_clk_setup setup1 = {
87 .clkout_nr = LITEX_CLK_TEST_CLK1,
88 .rate = LITEX_TEST_SINGLE_FREQ_VAL,
89 .duty = LITEX_TEST_SINGLE_DUTY_VAL,
90 .phase = LITEX_TEST_SINGLE_PHASE_VAL
91 };
92 struct litex_clk_setup setup2 = {
93 .clkout_nr = LITEX_CLK_TEST_CLK2,
94 .rate = LITEX_TEST_SINGLE_FREQ_VAL2,
95 .duty = LITEX_TEST_SINGLE_DUTY_VAL2,
96 .phase = LITEX_TEST_SINGLE_PHASE_VAL2,
97 };
98 uint32_t ret = 0;
99 clock_control_subsys_t sub_system1 = (clock_control_subsys_t)&setup1;
100 clock_control_subsys_t sub_system2 = (clock_control_subsys_t)&setup2;
101
102 printf("Single test\n");
103 ret = clock_control_on(dev, sub_system1);
104 if (ret != 0) {
105 return ret;
106 }
107 ret = clock_control_on(dev, sub_system2);
108 if (ret != 0) {
109 return ret;
110 }
111
112 litex_clk_test_getters(dev);
113
114 return 0;
115 }
116
litex_clk_test_freq(const struct device * dev)117 int litex_clk_test_freq(const struct device *dev)
118 {
119 struct litex_clk_setup setup = {
120 .clkout_nr = LITEX_CLK_TEST_CLK1,
121 .duty = LITEX_TEST_FREQUENCY_DUTY_VAL,
122 .phase = LITEX_TEST_FREQUENCY_PHASE_VAL
123 };
124 clock_control_subsys_t sub_system = (clock_control_subsys_t)&setup;
125 uint32_t i, ret = 0;
126
127 printf("Frequency test\n");
128
129 do {
130 for (i = LITEX_TEST_FREQUENCY_MIN; i < LITEX_TEST_FREQUENCY_MAX;
131 i += LITEX_TEST_FREQUENCY_STEP) {
132 setup.clkout_nr = LITEX_CLK_TEST_CLK1;
133 setup.rate = i;
134 sub_system = (clock_control_subsys_t)&setup;
135 /*
136 * Don't check for ENOTSUP here because it is expected.
137 * The reason is that set of possible frequencies for
138 * specific clock output depends on devicetree config
139 * (including margin) and also on other active clock
140 * outputs configuration. Some configurations may cause
141 * errors when the driver is trying to update one of
142 * the clkouts.
143 * Ignoring these errors ensure that
144 * test will be finished
145 *
146 */
147 ret = clock_control_on(dev, sub_system);
148 if (ret != 0 && ret != -ENOTSUP) {
149 return ret;
150 }
151 setup.clkout_nr = LITEX_CLK_TEST_CLK2;
152 ret = clock_control_on(dev, sub_system);
153 if (ret != 0) {
154 return ret;
155 }
156 k_sleep(K_MSEC(LITEX_TEST_FREQUENCY_DELAY_MS));
157 }
158 for (i = LITEX_TEST_FREQUENCY_MAX; i > LITEX_TEST_FREQUENCY_MIN;
159 i -= LITEX_TEST_FREQUENCY_STEP) {
160 setup.clkout_nr = LITEX_CLK_TEST_CLK1;
161 setup.rate = i;
162 sub_system = (clock_control_subsys_t)&setup;
163 ret = clock_control_on(dev, sub_system);
164 if (ret != 0 && ret != -ENOTSUP) {
165 return ret;
166 }
167 setup.clkout_nr = LITEX_CLK_TEST_CLK2;
168 ret = clock_control_on(dev, sub_system);
169 if (ret != 0) {
170 return ret;
171 }
172 k_sleep(K_MSEC(LITEX_TEST_FREQUENCY_DELAY_MS));
173 }
174 } while (LITEX_TEST_LOOP);
175
176 return 0;
177 }
178
litex_clk_test_phase(const struct device * dev)179 int litex_clk_test_phase(const struct device *dev)
180 {
181 struct litex_clk_setup setup1 = {
182 .clkout_nr = LITEX_CLK_TEST_CLK1,
183 .rate = LITEX_TEST_PHASE_FREQ_VAL,
184 .duty = LITEX_TEST_PHASE_DUTY_VAL,
185 .phase = 0
186 };
187 struct litex_clk_setup setup2 = {
188 .clkout_nr = LITEX_CLK_TEST_CLK2,
189 .rate = LITEX_TEST_PHASE_FREQ_VAL,
190 .duty = LITEX_TEST_PHASE_DUTY_VAL
191 };
192 clock_control_subsys_t sub_system1 = (clock_control_subsys_t)&setup1;
193 clock_control_subsys_t sub_system2 = (clock_control_subsys_t)&setup2;
194 uint32_t ret = 0;
195 int i;
196
197 printf("Phase test\n");
198
199 ret = clock_control_on(dev, sub_system1);
200 if (ret != 0 && ret != -ENOTSUP) {
201 return ret;
202 }
203
204 do {
205 for (i = LITEX_TEST_PHASE_MIN; i <= LITEX_TEST_PHASE_MAX;
206 i += LITEX_TEST_PHASE_STEP) {
207 setup2.phase = i;
208 sub_system2 = (clock_control_subsys_t)&setup2;
209 ret = clock_control_on(dev, sub_system2);
210 if (ret != 0) {
211 return ret;
212 }
213 k_sleep(K_MSEC(LITEX_TEST_PHASE_DELAY_MS));
214 }
215 } while (LITEX_TEST_LOOP);
216
217 return 0;
218 }
219
litex_clk_test_duty(const struct device * dev)220 int litex_clk_test_duty(const struct device *dev)
221 {
222 struct litex_clk_setup setup1 = {
223 .clkout_nr = LITEX_CLK_TEST_CLK1,
224 .rate = LITEX_TEST_DUTY_FREQ_VAL,
225 .phase = LITEX_TEST_DUTY_PHASE_VAL,
226 .duty = 0
227 };
228 struct litex_clk_setup setup2 = {
229 .clkout_nr = LITEX_CLK_TEST_CLK2,
230 .rate = LITEX_TEST_DUTY_FREQ_VAL,
231 .phase = LITEX_TEST_DUTY_PHASE_VAL,
232 .duty = 0
233 };
234 uint32_t ret = 0, i;
235 clock_control_subsys_t sub_system1 = (clock_control_subsys_t)&setup1;
236 clock_control_subsys_t sub_system2 = (clock_control_subsys_t)&setup2;
237
238 ret = clock_control_on(dev, sub_system1);
239 if (ret != 0 && ret != -ENOTSUP) {
240 return ret;
241 }
242 ret = clock_control_on(dev, sub_system2);
243 if (ret != 0 && ret != -ENOTSUP) {
244 return ret;
245 }
246
247 printf("Duty test\n");
248
249 do {
250 for (i = LITEX_TEST_DUTY_MIN; i <= LITEX_TEST_DUTY_MAX;
251 i += LITEX_TEST_DUTY_STEP) {
252 setup1.duty = i;
253 sub_system1 = (clock_control_subsys_t)&setup1;
254 ret = clock_control_on(dev, sub_system1);
255 if (ret != 0) {
256 return ret;
257 }
258 setup2.duty = 100 - i;
259 sub_system2 = (clock_control_subsys_t)&setup2;
260 ret = clock_control_on(dev, sub_system2);
261 if (ret != 0) {
262 return ret;
263 }
264 k_sleep(K_MSEC(LITEX_TEST_DUTY_DELAY_MS));
265 }
266 for (i = LITEX_TEST_DUTY_MAX; i > LITEX_TEST_DUTY_MIN;
267 i -= LITEX_TEST_DUTY_STEP) {
268 setup1.duty = i;
269 sub_system1 = (clock_control_subsys_t)&setup1;
270 ret = clock_control_on(dev, sub_system1);
271 if (ret != 0) {
272 return ret;
273 }
274 setup2.duty = 100 - i;
275 sub_system2 = (clock_control_subsys_t)&setup2;
276 ret = clock_control_on(dev, sub_system2);
277 if (ret != 0) {
278 return ret;
279 }
280 k_sleep(K_MSEC(LITEX_TEST_DUTY_DELAY_MS));
281 }
282 } while (LITEX_TEST_LOOP);
283
284 return 0;
285 }
286
litex_clk_test(const struct device * dev)287 int litex_clk_test(const struct device *dev)
288 {
289 int ret;
290
291 printf("Clock test\n");
292
293 switch (LITEX_TEST) {
294 case LITEX_TEST_DUTY:
295 ret = litex_clk_test_duty(dev);
296 break;
297 case LITEX_TEST_PHASE:
298 ret = litex_clk_test_phase(dev);
299 break;
300 case LITEX_TEST_FREQUENCY:
301 ret = litex_clk_test_freq(dev);
302 break;
303 case LITEX_TEST_SINGLE:
304 default:
305 ret = litex_clk_test_single(dev);
306 }
307 printf("Clock test done returning: %d\n", ret);
308 return ret;
309
310 }
311
main(void)312 int main(void)
313 {
314 const struct device *const dev = DEVICE_DT_GET(MMCM);
315
316 printf("Clock Control Example! %s\n", CONFIG_ARCH);
317
318 printf("device name: %s\n", dev->name);
319 if (!device_is_ready(dev)) {
320 printf("error: device %s is not ready\n", dev->name);
321 return 0;
322 }
323
324 printf("clock control device is %p, name is %s\n",
325 dev, dev->name);
326
327 litex_clk_test(dev);
328 return 0;
329 }
330