1 /*
2  * Copyright (c) 2025 Ambiq Micro Inc. <www.ambiq.com>
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include <zephyr/kernel.h>
8 #include <zephyr/drivers/flash.h>
9 #include <zephyr/drivers/mspi.h>
10 #include <zephyr/device.h>
11 #include <zephyr/devicetree.h>
12 #include <stdio.h>
13 #include <string.h>
14 
15 #include "mspi_ambiq.h"
16 
17 #if CONFIG_FLASH_MSPI
18 #define TARGET_DEVICE DT_ALIAS(flash0)
19 #elif CONFIG_MEMC_MSPI
20 #define TARGET_DEVICE DT_ALIAS(psram0)
21 #else
22 #error "Unsupported device type!!"
23 #endif
24 
25 #define MSPI_AMBIQ_TIMING_CONFIG_DT(n)                                                       \
26 	{                                                                                    \
27 		.ui8WriteLatency    = DT_PROP_BY_IDX(n, ambiq_timing_config, 0),             \
28 		.ui8TurnAround      = DT_PROP_BY_IDX(n, ambiq_timing_config, 1),             \
29 		.bTxNeg             = DT_PROP_BY_IDX(n, ambiq_timing_config, 2),             \
30 		.bRxNeg             = DT_PROP_BY_IDX(n, ambiq_timing_config, 3),             \
31 		.bRxCap             = DT_PROP_BY_IDX(n, ambiq_timing_config, 4),             \
32 		.ui32TxDQSDelay     = DT_PROP_BY_IDX(n, ambiq_timing_config, 5),             \
33 		.ui32RxDQSDelay     = DT_PROP_BY_IDX(n, ambiq_timing_config, 6),             \
34 	}
35 
36 #define MSPI_AMBIQ_TIMING_CONFIG_MASK_DT(n) DT_PROP(n, ambiq_timing_config_mask)
37 
main(void)38 int main(void)
39 {
40 	const struct device *tar_bus = DEVICE_DT_GET(DT_BUS(TARGET_DEVICE));
41 	const struct device *tar_dev = DEVICE_DT_GET(TARGET_DEVICE);
42 	struct mspi_dev_id dev_id = MSPI_DEVICE_ID_DT(TARGET_DEVICE);
43 #if CONFIG_MEMC_MSPI
44 	struct mspi_xip_cfg tar_xip_cfg = MSPI_XIP_CONFIG_DT(TARGET_DEVICE);
45 #endif
46 	struct mspi_ambiq_timing_cfg tar_timing_cfg = MSPI_AMBIQ_TIMING_CONFIG_DT(TARGET_DEVICE);
47 	uint32_t timing_cfg_mask = MSPI_AMBIQ_TIMING_CONFIG_MASK_DT(TARGET_DEVICE);
48 	struct mspi_ambiq_timing_scan scan;
49 
50 	if (!device_is_ready(tar_dev)) {
51 		printk("%s: device not ready.\n", tar_dev->name);
52 		return 1;
53 	}
54 
55 #if CONFIG_MEMC_MSPI
56 	if (!tar_xip_cfg.enable) {
57 		printk("Need to enable XIP for timing scan.\n");
58 		return 1;
59 	}
60 #endif
61 
62 	memset(&scan, 0, sizeof(struct mspi_ambiq_timing_scan));
63 	scan.range.txdqs_end  = 10;
64 	scan.range.rxdqs_end  = 31;
65 #if CONFIG_FLASH_MSPI
66 	scan.scan_type        = MSPI_AMBIQ_TIMING_SCAN_FLASH;
67 #elif CONFIG_MEMC_MSPI
68 	uint32_t base_addr    = DT_REG_ADDR_BY_IDX(DT_BUS(TARGET_DEVICE), 1);
69 
70 	scan.scan_type        = MSPI_AMBIQ_TIMING_SCAN_MEMC;
71 	scan.device_addr      = base_addr +
72 				tar_xip_cfg.address_offset +
73 				tar_xip_cfg.size / 2;
74 #endif
75 	scan.min_window       = 6;
76 
77 	if (mspi_ambiq_timing_scan(tar_dev, tar_bus, &dev_id, timing_cfg_mask,
78 				   (void *)&tar_timing_cfg, &scan)) {
79 		printk("Failed to timing scan\n");
80 		return 1;
81 	}
82 
83 	printf("==========================\n");
84 	return 0;
85 }
86