1 /*
2 * Copyright 2023 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 /*
8 * Based on DMIC driver sample, which is:
9 * Copyright (c) 2021 Nordic Semiconductor ASA
10 */
11
12 #include <zephyr/kernel.h>
13 #include <zephyr/audio/dmic.h>
14 #include <zephyr/ztest.h>
15
16 static const struct device *dmic_dev = DEVICE_DT_GET(DT_ALIAS(dmic_dev));
17
18 #if DT_HAS_COMPAT_STATUS_OKAY(nxp_dmic)
19 #define PDM_CHANNELS 4 /* Two L/R pairs of channels */
20 #define SAMPLE_BIT_WIDTH 16
21 #define BYTES_PER_SAMPLE sizeof(int16_t)
22 #define SLAB_ALIGN 4
23 #define MAX_SAMPLE_RATE 48000
24 #elif DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_pdm)
25 #define PDM_CHANNELS 2
26 #define SAMPLE_BIT_WIDTH 16
27 #define BYTES_PER_SAMPLE sizeof(int16_t)
28 #define SLAB_ALIGN 4
29 #define MAX_SAMPLE_RATE 48000
30 #else
31 #error "Unsupported DMIC device"
32 #endif
33
34 /* Milliseconds to wait for a block to be read. */
35 #define READ_TIMEOUT 1000
36 /* Size of a block for 100 ms of audio data. */
37 #if defined(CONFIG_COVERAGE)
38 /* Use smaller buffer in coverage mode. */
39 #define BLOCK_SIZE(_sample_rate, _number_of_channels) \
40 (BYTES_PER_SAMPLE * (_sample_rate / 100) * _number_of_channels)
41 #else
42 #define BLOCK_SIZE(_sample_rate, _number_of_channels) \
43 (BYTES_PER_SAMPLE * (_sample_rate / 10) * _number_of_channels)
44 #endif
45
46 /* Driver will allocate blocks from this slab to receive audio data into them.
47 * Application, after getting a given block from the driver and processing its
48 * data, needs to free that block.
49 */
50 #define MAX_BLOCK_SIZE BLOCK_SIZE(MAX_SAMPLE_RATE, PDM_CHANNELS)
51 #define BLOCK_COUNT 8
52 K_MEM_SLAB_DEFINE_STATIC(mem_slab, MAX_BLOCK_SIZE, BLOCK_COUNT, SLAB_ALIGN);
53
54 static struct pcm_stream_cfg pcm_stream = {
55 .pcm_width = SAMPLE_BIT_WIDTH,
56 .mem_slab = &mem_slab,
57 };
58 static struct dmic_cfg dmic_cfg = {
59 .io = {
60 /* These fields can be used to limit the PDM clock
61 * configurations that the driver is allowed to use
62 * to those supported by the microphone.
63 */
64 .min_pdm_clk_freq = 1000000,
65 .max_pdm_clk_freq = 3500000,
66 .min_pdm_clk_dc = 40,
67 .max_pdm_clk_dc = 60,
68 },
69 .streams = &pcm_stream,
70 .channel = {
71 .req_num_streams = 1,
72 },
73 };
74
75 /* Verify that dmic_trigger fails when DMIC is not configured
76 * this test must run first, before DMIC has been configured
77 */
ZTEST(dmic,test_0_start_fail)78 ZTEST(dmic, test_0_start_fail)
79 {
80 int ret;
81
82 zassert_true(device_is_ready(dmic_dev), "DMIC device is not ready");
83 ret = dmic_trigger(dmic_dev, DMIC_TRIGGER_START);
84 zassert_not_equal(ret, 0, "DMIC trigger should fail when DMIC is not configured");
85 }
86
do_pdm_transfer(const struct device * dmic,struct dmic_cfg * cfg)87 static int do_pdm_transfer(const struct device *dmic,
88 struct dmic_cfg *cfg)
89 {
90 int ret;
91 void *buffer;
92 uint32_t size;
93
94 TC_PRINT("PCM output rate: %u, channels: %u\n",
95 cfg->streams[0].pcm_rate, cfg->channel.req_num_chan);
96
97 ret = dmic_configure(dmic, cfg);
98 if (ret < 0) {
99 TC_PRINT("DMIC configuration failed: %d\n", ret);
100 return ret;
101 }
102
103 /* Check that the driver is properly populating the "act*" fields */
104 zassert_equal(cfg->channel.act_num_chan,
105 cfg->channel.req_num_chan,
106 "DMIC configure should populate act_num_chan field");
107 zassert_equal(cfg->channel.act_chan_map_lo,
108 cfg->channel.req_chan_map_lo,
109 "DMIC configure should populate act_chan_map_lo field");
110 zassert_equal(cfg->channel.act_chan_map_hi,
111 cfg->channel.req_chan_map_hi,
112 "DMIC configure should populate act_chan_map_hi field");
113 ret = dmic_trigger(dmic, DMIC_TRIGGER_START);
114 if (ret < 0) {
115 TC_PRINT("DMIC start trigger failed: %d\n", ret);
116 return ret;
117 }
118
119 /* We read more than the total BLOCK_COUNT to insure the DMIC
120 * driver correctly reallocates memory slabs as it exhausts existing
121 * ones.
122 */
123 for (int i = 0; i < (2 * BLOCK_COUNT); i++) {
124 ret = dmic_read(dmic, 0, &buffer, &size, READ_TIMEOUT);
125 if (ret < 0) {
126 TC_PRINT("DMIC read failed: %d\n", ret);
127 return ret;
128 }
129
130 TC_PRINT("%d - got buffer %p of %u bytes\n", i, buffer, size);
131 k_mem_slab_free(&mem_slab, buffer);
132 }
133
134 ret = dmic_trigger(dmic, DMIC_TRIGGER_STOP);
135 if (ret < 0) {
136 TC_PRINT("DMIC stop trigger failed: %d\n", ret);
137 return ret;
138 }
139 return 0;
140 }
141
142
143 /* Verify that the DMIC can transfer from a single channel */
ZTEST(dmic,test_single_channel)144 ZTEST(dmic, test_single_channel)
145 {
146 dmic_cfg.channel.req_num_chan = 1;
147 dmic_cfg.channel.req_chan_map_lo =
148 dmic_build_channel_map(0, 0, PDM_CHAN_LEFT);
149 dmic_cfg.streams[0].pcm_rate = MAX_SAMPLE_RATE;
150 dmic_cfg.streams[0].block_size =
151 BLOCK_SIZE(dmic_cfg.streams[0].pcm_rate,
152 dmic_cfg.channel.req_num_chan);
153 zassert_equal(do_pdm_transfer(dmic_dev, &dmic_cfg), 0,
154 "Single channel transfer failed");
155 }
156
157 /* Verify that the DMIC can transfer from a L/R channel pair */
ZTEST(dmic,test_stereo_channel)158 ZTEST(dmic, test_stereo_channel)
159 {
160 dmic_cfg.channel.req_num_chan = 2;
161 dmic_cfg.channel.req_chan_map_lo =
162 dmic_build_channel_map(0, 0, PDM_CHAN_LEFT) |
163 dmic_build_channel_map(1, 0, PDM_CHAN_RIGHT);
164 dmic_cfg.streams[0].pcm_rate = MAX_SAMPLE_RATE;
165 dmic_cfg.streams[0].block_size =
166 BLOCK_SIZE(dmic_cfg.streams[0].pcm_rate,
167 dmic_cfg.channel.req_num_chan);
168 zassert_equal(do_pdm_transfer(dmic_dev, &dmic_cfg), 0,
169 "L/R channel transfer failed");
170 dmic_cfg.channel.req_chan_map_lo =
171 dmic_build_channel_map(0, 0, PDM_CHAN_RIGHT) |
172 dmic_build_channel_map(1, 0, PDM_CHAN_LEFT);
173 zassert_equal(do_pdm_transfer(dmic_dev, &dmic_cfg), 0,
174 "R/L channel transfer failed");
175 }
176
177 /* Test DMIC with maximum number of channels */
ZTEST(dmic,test_max_channel)178 ZTEST(dmic, test_max_channel)
179 {
180 enum pdm_lr lr;
181 uint8_t pdm_hw_chan;
182
183 dmic_cfg.channel.req_num_chan = PDM_CHANNELS;
184 dmic_cfg.channel.req_chan_map_lo = 0;
185 dmic_cfg.channel.req_chan_map_hi = 0;
186 for (uint8_t i = 0; i < PDM_CHANNELS; i++) {
187 lr = ((i % 2) == 0) ? PDM_CHAN_LEFT : PDM_CHAN_RIGHT;
188 pdm_hw_chan = i >> 1;
189 if (i < 4) {
190 dmic_cfg.channel.req_chan_map_lo |=
191 dmic_build_channel_map(i, pdm_hw_chan, lr);
192 } else {
193 dmic_cfg.channel.req_chan_map_hi |=
194 dmic_build_channel_map(i, pdm_hw_chan, lr);
195 }
196 }
197
198 dmic_cfg.streams[0].pcm_rate = MAX_SAMPLE_RATE;
199 dmic_cfg.streams[0].block_size =
200 BLOCK_SIZE(dmic_cfg.streams[0].pcm_rate,
201 dmic_cfg.channel.req_num_chan);
202 zassert_equal(do_pdm_transfer(dmic_dev, &dmic_cfg), 0,
203 "Maximum channel transfer failed");
204 }
205
206 /* Test pausing and restarting a channel */
ZTEST(dmic,test_pause_restart)207 ZTEST(dmic, test_pause_restart)
208 {
209 int ret, i;
210 void *buffer;
211 uint32_t size;
212
213 dmic_cfg.channel.req_num_chan = 1;
214 dmic_cfg.channel.req_chan_map_lo =
215 dmic_build_channel_map(0, 0, PDM_CHAN_LEFT);
216 dmic_cfg.streams[0].pcm_rate = MAX_SAMPLE_RATE;
217 dmic_cfg.streams[0].block_size =
218 BLOCK_SIZE(dmic_cfg.streams[0].pcm_rate,
219 dmic_cfg.channel.req_num_chan);
220 ret = dmic_configure(dmic_dev, &dmic_cfg);
221 zassert_equal(ret, 0, "DMIC configure failed");
222
223 /* Start the DMIC, and pause it immediately */
224 ret = dmic_trigger(dmic_dev, DMIC_TRIGGER_START);
225 zassert_equal(ret, 0, "DMIC start failed");
226 ret = dmic_trigger(dmic_dev, DMIC_TRIGGER_PAUSE);
227 zassert_equal(ret, 0, "DMIC pause failed");
228 /* There may be some buffers in the DMIC queue, but a read
229 * should eventually time out while it is paused
230 */
231 for (i = 0; i < (2 * BLOCK_COUNT); i++) {
232 ret = dmic_read(dmic_dev, 0, &buffer, &size, READ_TIMEOUT);
233 if (ret < 0) {
234 break;
235 }
236 k_mem_slab_free(&mem_slab, buffer);
237 }
238 zassert_not_equal(ret, 0, "DMIC is paused, reads should timeout");
239 TC_PRINT("Queue drained after %d reads\n", i);
240 /* Unpause the DMIC */
241 ret = dmic_trigger(dmic_dev, DMIC_TRIGGER_RELEASE);
242 zassert_equal(ret, 0, "DMIC release failed");
243 /* Reads should not timeout now */
244 for (i = 0; i < (2 * BLOCK_COUNT); i++) {
245 ret = dmic_read(dmic_dev, 0, &buffer, &size, READ_TIMEOUT);
246 if (ret < 0) {
247 break;
248 }
249 k_mem_slab_free(&mem_slab, buffer);
250 }
251 zassert_equal(ret, 0, "DMIC is active, reads should succeed");
252 TC_PRINT("%d reads completed\n", (2 * BLOCK_COUNT));
253 /* Stop the DMIC, and repeat the same tests */
254 ret = dmic_trigger(dmic_dev, DMIC_TRIGGER_STOP);
255 zassert_equal(ret, 0, "DMIC stop failed");
256 /* Versus a pause, DMIC reads should immediately stop once DMIC times
257 * out
258 */
259 ret = dmic_read(dmic_dev, 0, &buffer, &size, READ_TIMEOUT);
260 zassert_not_equal(ret, 0, "DMIC read should timeout when DMIC is stopped");
261 ret = dmic_trigger(dmic_dev, DMIC_TRIGGER_START);
262 zassert_equal(ret, 0, "DMIC restart failed");
263 /* Reads should not timeout now */
264 for (i = 0; i < (2 * BLOCK_COUNT); i++) {
265 ret = dmic_read(dmic_dev, 0, &buffer, &size, READ_TIMEOUT);
266 if (ret < 0) {
267 break;
268 }
269 k_mem_slab_free(&mem_slab, buffer);
270 }
271 zassert_equal(ret, 0, "DMIC is active, reads should succeed");
272 TC_PRINT("%d reads completed\n", (2 * BLOCK_COUNT));
273 /* Test is over. Stop the DMIC */
274 ret = dmic_trigger(dmic_dev, DMIC_TRIGGER_STOP);
275 zassert_equal(ret, 0, "DMIC stop failed");
276 }
277
278 /* Verify that channel map without adjacent L/R pairs fails */
ZTEST(dmic,test_bad_pair)279 ZTEST(dmic, test_bad_pair)
280 {
281 int ret;
282
283 dmic_cfg.channel.req_num_chan = 2;
284 dmic_cfg.channel.req_chan_map_lo =
285 dmic_build_channel_map(0, 0, PDM_CHAN_RIGHT) |
286 dmic_build_channel_map(1, 0, PDM_CHAN_RIGHT);
287 dmic_cfg.streams[0].pcm_rate = MAX_SAMPLE_RATE;
288 dmic_cfg.streams[0].block_size =
289 BLOCK_SIZE(dmic_cfg.streams[0].pcm_rate,
290 dmic_cfg.channel.req_num_chan);
291 ret = dmic_configure(dmic_dev, &dmic_cfg);
292 zassert_not_equal(ret, 0, "DMIC configure should fail with "
293 "two of same channel in map");
294
295 dmic_cfg.channel.req_num_chan = 2;
296 dmic_cfg.channel.req_chan_map_lo =
297 dmic_build_channel_map(0, 0, PDM_CHAN_RIGHT) |
298 dmic_build_channel_map(1, 1, PDM_CHAN_LEFT);
299 ret = dmic_configure(dmic_dev, &dmic_cfg);
300 zassert_not_equal(ret, 0, "DMIC configure should fail with "
301 "non adjacent channels in map");
302 }
303
304 ZTEST_SUITE(dmic, NULL, NULL, NULL, NULL, NULL);
305