1/*
2 * Copyright (c) 2025 Renesas Electronics Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <zephyr/dt-bindings/pwm/pwm.h>
8
9/ {
10	aliases {
11		i2s-node0 = &i2s0;
12	};
13};
14
15&pinctrl {
16	ssie0_default: ssie0_default {
17		group1 {
18			/* SSI_BCK SSI_LRCK SSI_TX SSI_RX */
19			psels = <RA_PSEL(RA_PSEL_SSIE, 4, 3)>,
20				<RA_PSEL(RA_PSEL_SSIE, 1, 13)>,
21				<RA_PSEL(RA_PSEL_SSIE, 4, 5)>,
22				<RA_PSEL(RA_PSEL_SSIE, 4, 6)>;
23			drive-strength = "high";
24		};
25	};
26
27	pwm2_default: pwm2_default {
28		group1 {
29			/* GTIOC2A */
30			psels = <RA_PSEL(RA_PSEL_GPT1, 1, 3)>;
31		};
32	};
33};
34
35&i2s0 {
36	pinctrl-0 = <&ssie0_default>;
37	pinctrl-names = "default";
38	interrupts = <93 12>, <94 12>, <95 12>;
39	interrupt-names = "ssi_txi", "ssi_rxi", "ssi_if";
40	status = "okay";
41	clocks = <&pclkb MSTPC 8>, <&ssi_internal_clock 0>;
42	clock-names = "pclk", "audio-clock";
43};
44
45&pwm2 {
46	pinctrl-0 = <&pwm2_default>;
47	pinctrl-names = "default";
48	interrupts = <91 12>, <92 12>;
49	interrupt-names = "gtioca", "overflow";
50	status = "okay";
51
52	ssi_internal_clock: pwmclock {
53		status = "okay";
54		compatible = "pwm-clock";
55		#clock-cells = <1>;
56		pwms = <&pwm2 0 PWM_HZ(512000) PWM_POLARITY_NORMAL>;
57	};
58};
59